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authorPeter Daifuku <pdaifuku@nvidia.com>2017-10-13 20:06:30 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-25 23:24:10 -0400
commit6bf40e523740279761f3fdc3d84000acc2f62aba (patch)
treebf56295c292b5ee9bee232141bc0ebd262f02225 /drivers/gpu/nvgpu/gp10b/gr_gp10b.h
parent0dcf0ede812aa55aa106a5e6c2f86216fcbfd5e0 (diff)
gpu: nvgpu: add max_css_buffer_size characteristic
Add max_css_buffer_size to gpu characteristics. In the virtual case, the size of the cycle stats snapshot buffer is constrained by the size of the mempool shared between the guest OS and the RM server, so tools need to find out what is the maximum size allowed. In the native case, we return 0xffffffff to indicate that the buffer size is unbounded (subject to memory availability), in the virtual case we return the size of the mempool. Also collapse native init_cyclestats functions to a single version, as each chip had identical versions of the code. JIRA ESRM-54 Bug 200296210 Change-Id: I71764d32c6e71a0d101bd40f274eaa4bea3e5b11 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1578930 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.h')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 9ddc0375..a537f147 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -115,7 +115,6 @@ void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
115 struct channel_ctx_gk20a *ch_ctx, 115 struct channel_ctx_gk20a *ch_ctx,
116 u64 addr, u64 size, bool patch); 116 u64 addr, u64 size, bool patch);
117int gr_gp10b_load_smid_config(struct gk20a *g); 117int gr_gp10b_load_smid_config(struct gk20a *g);
118void gr_gp10b_init_cyclestats(struct gk20a *g);
119void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); 118void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
120void gr_gp10b_get_access_map(struct gk20a *g, 119void gr_gp10b_get_access_map(struct gk20a *g,
121 u32 **whitelist, int *num_entries); 120 u32 **whitelist, int *num_entries);