gpu: nvgpu: implement set_gpc_tpc_mask for gp10b

Bug 200137963

Change-Id: Ibd09b206620e6d6826586bb40e1125fc178dd8e4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797151
(cherry picked from commit 343c4704564f4b4f22a943a94e66d2c83f63a28f)
Reviewed-on: http://git-master/r/808241
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 1a50d29a..d61ac5bb 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -15,6 +15,7 @@
 
 #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
 #include <linux/delay.h>
+#include <linux/tegra-fuse.h>
 
 #include "gk20a/gr_gk20a.h"
 
@@ -1006,6 +1007,19 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g)
 #endif
 }
 
+static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
+{
+        tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0);
+        tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0);
+
+        if (g->gr.gpc_tpc_mask[gpc_index] == 0x1)
+                tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0);
+        else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2)
+                tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
+        else
+                tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
+}
+
 void gp10b_init_gr(struct gpu_ops *gops)
 {
         gm20b_init_gr(gops);
@@ -1034,4 +1048,5 @@ void gp10b_init_gr(struct gpu_ops *gops)
         gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs;
         gops->gr.wait_empty = gr_gp10b_wait_empty;
         gops->gr.init_cyclestats = gr_gp10b_init_cyclestats;
+        gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask;
 }