gpu: nvgpu: Implement SET_RD_COALESCE

Implement SW method SET_RD_COALESCE to implement correct handling
of texture read coalescing.

Bug 200223870

Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1271303
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

1 files changed, 7 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 9de7d675..45820c5c 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP10B GPU GR
  *
- * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -629,6 +629,9 @@ static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
                 case NVC0C0_SET_SHADER_EXCEPTIONS:
                         gk20a_gr_set_shader_exceptions(g, data);
                         break;
+                case NVC0C0_SET_RD_COALESCE:
+                        gr_gm20b_set_rd_coalesce(g, data);
+                        break;
                 default:
                         goto fail;
                 }
@@ -651,6 +654,9 @@ static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
                 case NVC097_SET_COALESCE_BUFFER_SIZE:
                         gr_gp10b_set_coalesce_buffer_size(g, data);
                         break;
+                case NVC097_SET_RD_COALESCE:
+                        gr_gm20b_set_rd_coalesce(g, data);
+                        break;
                 default:
                         goto fail;
                 }