gpu: nvgpu: gp10b: add ECC stats sysfs nodes

Add sysfs nodes for querying ECC single/double bit error counts.

Bug 1699676

Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935363
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 145 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index c66dea92..90d0ce8d 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -80,6 +80,13 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
                         "Single bit error detected in SM LRF!");
+
+                g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] +=
+                        gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset);
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset,
+                        0);
         }
         if ( (lrf_ecc_status &
                 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) ||
@@ -92,6 +99,13 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
                         "Double bit error detected in SM LRF!");
+
+                g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] +=
+                        gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset);
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset,
+                        0);
         }
         gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
                         lrf_ecc_status);
@@ -107,17 +121,42 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) ||
                 (shm_ecc_status &
                 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) {
+                u32 ecc_stats_reg_val;
 
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
                         "Single bit error detected in SM SHM!");
+
+                ecc_stats_reg_val =
+                        gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
+                g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] +=
+                        gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val);
+                g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] +=
+                        gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() |
+                                        gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m());
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
+                        ecc_stats_reg_val);
         }
         if ( (shm_ecc_status &
                 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) ||
                 (shm_ecc_status &
                 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) {
+                u32 ecc_stats_reg_val;
 
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
                         "Double bit error detected in SM SHM!");
+
+                ecc_stats_reg_val =
+                        gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
+                g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] +=
+                        gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m());
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
+                        ecc_stats_reg_val);
         }
         gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset,
                         shm_ecc_status);
@@ -133,6 +172,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
         u32 offset = proj_gpc_stride_v() * gpc +
                      proj_tpc_in_gpc_stride_v() * tpc;
         u32 esr;
+        u32 ecc_stats_reg_val;
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
 
@@ -143,10 +183,114 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
         if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) {
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
                         "Single bit error detected in TEX!");
+
+                /* Pipe 0 counters */
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
+                        gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
+                g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
+                        ecc_stats_reg_val);
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
+                g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
+                        ecc_stats_reg_val);
+
+
+                /* Pipe 1 counters */
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
+                        gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
+                g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
+                        ecc_stats_reg_val);
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
+                g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
+                        ecc_stats_reg_val);
+
+
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
+                        gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
         }
         if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) {
                 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
                         "Double bit error detected in TEX!");
+
+                /* Pipe 0 counters */
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
+                        gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
+                g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
+                        ecc_stats_reg_val);
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
+                g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
+                        ecc_stats_reg_val);
+
+
+                /* Pipe 1 counters */
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
+                        gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
+                g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
+                        ecc_stats_reg_val);
+
+                ecc_stats_reg_val = gk20a_readl(g,
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
+                g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] +=
+                                gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
+                ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
+                        ecc_stats_reg_val);
+
+
+                gk20a_writel(g,
+                        gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
+                        gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
         }
 
         gk20a_writel(g,
@@ -1594,4 +1738,5 @@ void gp10b_init_gr(struct gpu_ops *gops)
         gops->gr.pre_process_sm_exception =
                 gr_gp10b_pre_process_sm_exception;
         gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error;
+        gops->gr.create_gr_sysfs = gr_gp10b_create_sysfs;
 }