gpu: nvgpu: ZBC update without idle

Do ZBC updates without forcing engine idle first.

Bug 1698013

Change-Id: I188563dd60ba511b087e9b9bdacd7f9445efd7a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829146

1 files changed, 9 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index c801a2b8..defda1c3 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -210,14 +210,18 @@ static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
         gr->zbc_col_tbl[index].format = color_val->format;
         gr->zbc_col_tbl[index].ref_cnt++;
 
-        gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), color_val->color_ds[0]);
-        gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), color_val->color_ds[1]);
-        gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), color_val->color_ds[2]);
-        gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]);
+        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
+                           color_val->color_ds[0]);
+        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
+                           color_val->color_ds[1]);
+        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index),
+                           color_val->color_ds[2]);
+        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
+                           color_val->color_ds[3]);
         zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3));
         zbc_c &= ~(0x7f << ((index % 4) * 7));
         zbc_c |= color_val->format << ((index % 4) * 7);
-        gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c);
+        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c);
 
         return 0;
 }