gpu: nvgpu: add clear_sm_hww gr ops

Required for multiple SM support and t19x SM
register address changes

JIRA GPUT19X-75

Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 27d609d1..4ff306e0 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1835,7 +1835,8 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
                         /* reset the HWW errors after locking down */
                         global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g,
                                                         gpc, tpc, sm);
-                        gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
+                        g->ops.gr.clear_sm_hww(g,
+                                                gpc, tpc, sm, global_esr_copy);
                         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
                                         "CILP: HWWs cleared for gpc %d tpc %d\n",
                                         gpc, tpc);