nvgpu: gv11b: Rearrange gr function

Moved gv11b_detect_ecc_enabled_units function
from gv11b.c to gr_gv11b.c, as this is being
used only in gr_gv11b file.

In order to avoid GR code touching fuse registers,
as it need to include fuse HW headers in GR code,
introduced two fuse HALs which are being called
from GR code. is_opt_ecc_enable for checking
whether ecc enable bit is set in fuse register
and is_opt_feature_overide_disable for checking
whether feature override disable bit is set in
fuse register.

Initialized fuse HAL functions for chips that
make use of those HAL functions.

JIRA NVGPU-615

Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775564
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 7 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 424c8490..16eddeca 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -43,7 +43,6 @@
 #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
-#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 
 #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000
 
@@ -2022,11 +2021,14 @@ u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
 
 u32 get_ecc_override_val(struct gk20a *g)
 {
-        u32 val;
+        bool en = false;
 
-        val = gk20a_readl(g, fuse_opt_ecc_en_r());
-        if (val)
-                return gk20a_readl(g, gr_fecs_feature_override_ecc_r());
+        if (g->ops.fuse.is_opt_ecc_enable) {
+                en = g->ops.fuse.is_opt_ecc_enable(g);
+                if (en) {
+                        return gk20a_readl(g, gr_fecs_feature_override_ecc_r());
+                }
+        }
 
         return 0;
 }