diff options
author | Seema Khowala <seemaj@nvidia.com> | 2018-12-13 14:02:11 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2019-02-22 21:59:18 -0500 |
commit | c9d4df288d51e4776188a25a6a2bb26ddd897a20 (patch) | |
tree | de70d1fa9da9bd79e783d24db5953c74f5d15fb8 /drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |
parent | d975bda39876b288479ef5d72cb0495fe1c85c6b (diff) |
gpu: nvgpu: remove code for ch not bound to tsg
- Remove handling for channels that are no more bound to tsg
as channel could be referenceable but no more part of a tsg
- Use tsg_gk20a_from_ch to get pointer to tsg for a given channel
- Clear unhandled gr interrupts
Bug 2429295
JIRA NVGPU-1580
Change-Id: I9da43a2bc9a0282c793b9f301eaf8e8604f91d70
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972492
(cherry picked from commit 013ca60edd97e7719e389b3048fed9b165277251
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/2018262
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a3655146..8d02c8f6 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1691,6 +1691,14 @@ void gr_gp10b_get_access_map(struct gk20a *g, | |||
1691 | static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) | 1691 | static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) |
1692 | { | 1692 | { |
1693 | int ret = 0; | 1693 | int ret = 0; |
1694 | struct tsg_gk20a *tsg; | ||
1695 | |||
1696 | tsg = tsg_gk20a_from_ch(fault_ch); | ||
1697 | if (tsg == NULL) { | ||
1698 | nvgpu_err(g, "CILP: chid: %d is not bound to tsg", | ||
1699 | fault_ch->chid); | ||
1700 | return -EINVAL; | ||
1701 | } | ||
1694 | 1702 | ||
1695 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); | 1703 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); |
1696 | 1704 | ||
@@ -1711,18 +1719,11 @@ static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a | |||
1711 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); | 1719 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); |
1712 | 1720 | ||
1713 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1721 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1714 | "CILP: tsgid: 0x%x", fault_ch->tsgid); | 1722 | "CILP: tsgid: 0x%x", tsg->tsgid); |
1715 | 1723 | ||
1716 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { | 1724 | gk20a_fifo_issue_preempt(g, tsg->tsgid, true); |
1717 | gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); | 1725 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1718 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | ||
1719 | "CILP: preempted tsg"); | 1726 | "CILP: preempted tsg"); |
1720 | } else { | ||
1721 | gk20a_fifo_issue_preempt(g, fault_ch->chid, false); | ||
1722 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | ||
1723 | "CILP: preempted channel"); | ||
1724 | } | ||
1725 | |||
1726 | return ret; | 1727 | return ret; |
1727 | } | 1728 | } |
1728 | 1729 | ||