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authorPeter Daifuku <pdaifuku@nvidia.com>2017-11-08 22:13:29 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-13 21:19:20 -0500
commitc9419732776a3f31b3c1ace0cd113151f3a4d7cd (patch)
treeffe4252f735d75d46bed02ee9f61fbbd11677e4d /drivers/gpu/nvgpu/gp10b/gr_gp10b.c
parentc0a461dbbccf56681ff531e7e4c8f5fb01c3e2cf (diff)
gpu: nvgpu: ctx_patch_write fixes
- Add update_patch_count parameter to ctx_patch_write_begin/end functions If True, the main_image_patch_count register will be updated. Previously, the patch count would be updated if the cpu_va for the graphics context was non-NULL, but this only works for sysmem (cpu_va is always 0 for vidmem) - Remove unused patch parameter for the commit_global_timeslice functions JIRA ESRM-74 Bug 2012077 Change-Id: I35d0a9eb48669a227833bba1d2e63e9fe8fd8aa9 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594790 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 24b22a7d..c9b2f859 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1224,7 +1224,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
1224 gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va); 1224 gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va);
1225 } 1225 }
1226 1226
1227 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); 1227 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true);
1228 if (err) { 1228 if (err) {
1229 nvgpu_err(g, "can't map patch context"); 1229 nvgpu_err(g, "can't map patch context");
1230 goto out; 1230 goto out;
@@ -1277,7 +1277,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
1277 cbes_reserve), 1277 cbes_reserve),
1278 true); 1278 true);
1279 1279
1280 gr_gk20a_ctx_patch_write_end(g, ch_ctx); 1280 gr_gk20a_ctx_patch_write_end(g, ch_ctx, true);
1281 } 1281 }
1282 1282
1283out: 1283out:
@@ -2254,13 +2254,13 @@ int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
2254 g->ops.gr.update_ctxsw_preemption_mode(ch->g, 2254 g->ops.gr.update_ctxsw_preemption_mode(ch->g,
2255 ch_ctx, mem); 2255 ch_ctx, mem);
2256 2256
2257 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); 2257 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true);
2258 if (err) { 2258 if (err) {
2259 nvgpu_err(g, "can't map patch context"); 2259 nvgpu_err(g, "can't map patch context");
2260 goto enable_ch; 2260 goto enable_ch;
2261 } 2261 }
2262 g->ops.gr.commit_global_cb_manager(g, ch, true); 2262 g->ops.gr.commit_global_cb_manager(g, ch, true);
2263 gr_gk20a_ctx_patch_write_end(g, ch_ctx); 2263 gr_gk20a_ctx_patch_write_end(g, ch_ctx, true);
2264 } 2264 }
2265 2265
2266enable_ch: 2266enable_ch: