gpu: nvgpu: Rename gk20a_mem_* functions

Rename the functions used for mem_desc access to nvgpu_mem_*.

JIRA NVGPU-12

Change-Id: Ibfdc1112d43f0a125e4487c250e3f977ffd2cd75
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1323325
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 22 insertions, 22 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 95590e40..fc831e75 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1039,51 +1039,51 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
 {
         struct mem_desc *mem = &gr_ctx->mem;
 
-        if (gk20a_mem_begin(g, mem)) {
+        if (nvgpu_mem_begin(g, mem)) {
                 WARN_ON("Cannot map context");
                 return;
         }
         gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                                 ctxsw_prog_main_image_magic_value_o()),
                 ctxsw_prog_main_image_magic_value_v_value_v());
 
         gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                                 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()));
 
         gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                                 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()));
 
         gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                                 ctxsw_prog_main_image_context_timestamp_buffer_control_o()));
 
         gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_num_save_ops_o()));
         gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_num_wfi_save_ops_o()));
         gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_num_cta_save_ops_o()));
         gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_num_gfxp_save_ops_o()));
         gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_num_cilp_save_ops_o()));
         gk20a_err(dev_from_gk20a(g),
                 "image gfx preemption option (GFXP is 1) %x\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_graphics_preemption_options_o()));
         gk20a_err(dev_from_gk20a(g),
                 "image compute preemption option (CTA is 1) %x\n",
-                gk20a_mem_rd(g, mem,
+                nvgpu_mem_rd(g, mem,
                         ctxsw_prog_main_image_compute_preemption_options_o()));
-        gk20a_mem_end(g, mem);
+        nvgpu_mem_end(g, mem);
 }
 
 static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
@@ -1123,21 +1123,21 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
 
         if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) {
                 gk20a_dbg_info("GfxP: %x", gfxp_preempt_option);
-                gk20a_mem_wr(g, mem,
+                nvgpu_mem_wr(g, mem,
                                 ctxsw_prog_main_image_graphics_preemption_options_o(),
                                 gfxp_preempt_option);
         }
 
         if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) {
                 gk20a_dbg_info("CILP: %x", cilp_preempt_option);
-                gk20a_mem_wr(g, mem,
+                nvgpu_mem_wr(g, mem,
                                 ctxsw_prog_main_image_compute_preemption_options_o(),
                                 cilp_preempt_option);
         }
 
         if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CTA) {
                 gk20a_dbg_info("CTA: %x", cta_preempt_option);
-                gk20a_mem_wr(g, mem,
+                nvgpu_mem_wr(g, mem,
                                 ctxsw_prog_main_image_compute_preemption_options_o(),
                                 cta_preempt_option);
         }
@@ -1147,7 +1147,7 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
                 u32 size;
                 u32 cbes_reserve;
 
-                gk20a_mem_wr(g, mem,
+                nvgpu_mem_wr(g, mem,
                                 ctxsw_prog_main_image_full_preemption_ptr_o(),
                                 gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8);
 
@@ -2077,7 +2077,7 @@ static int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
 
         gr_ctx->boosted_ctx = boost;
 
-        if (gk20a_mem_begin(g, mem))
+        if (nvgpu_mem_begin(g, mem))
                 return -ENOMEM;
 
         err = gk20a_disable_channel_tsg(g, ch);
@@ -2096,7 +2096,7 @@ static int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
 enable_ch:
         gk20a_enable_channel_tsg(g, ch);
 unmap_ctx:
-        gk20a_mem_end(g, mem);
+        nvgpu_mem_end(g, mem);
 
         return err;
 }
@@ -2107,7 +2107,7 @@ static void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct mem_desc *mem,
 
         v = ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(
                 gr_ctx->boosted_ctx);
-        gk20a_mem_wr(g, mem, ctxsw_prog_main_image_pmu_options_o(), v);
+        nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pmu_options_o(), v);
 }
 
 static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
@@ -2164,7 +2164,7 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
                 }
         }
 
-        if (gk20a_mem_begin(g, mem))
+        if (nvgpu_mem_begin(g, mem))
                 return -ENOMEM;
 
         err = gk20a_disable_channel_tsg(g, ch);
@@ -2191,7 +2191,7 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
 enable_ch:
         gk20a_enable_channel_tsg(g, ch);
 unmap_ctx:
-        gk20a_mem_end(g, mem);
+        nvgpu_mem_end(g, mem);
 
         return err;
 }