gpu: nvgpu: Add L2 register read-backs following writes

LTC register write is followed by a register read
and if data doesn't match code will report the error.

Renamed existing nvgpu_writel_check function as
nvgpu_writel_loop as it loops until the write get success.

nvgpu_writel_check function write and read back and
compare the data.

Bug 2039150

Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762344
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 6249992a..424c8490 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -537,18 +537,18 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
         gr->zbc_col_tbl[index].format = color_val->format;
         gr->zbc_col_tbl[index].ref_cnt++;
 
-        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
+        nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
                            color_val->color_ds[0]);
-        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
+        nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
                            color_val->color_ds[1]);
-        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index),
+        nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_b_r(index),
                            color_val->color_ds[2]);
-        gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
+        nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
                            color_val->color_ds[3]);
         zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3));
         zbc_c &= ~(0x7f << ((index % 4) * 7));
         zbc_c |= color_val->format << ((index % 4) * 7);
-        gk20a_writel_check(g, zbc_c_format_reg + (index & ~3), zbc_c);
+        nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3), zbc_c);
 
         return 0;
 }