gpu: nvgpu: null check for fault_ch

gk20a_gr_get_channel_from_ctx() could return NULL as a result
fault_ch could be null

JIRA GPUT19X-7

Change-Id: I2c8f099f63f30e576ecd221e3bec25070b026ced
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1323252
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 6de6b599..7f43a6ce 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1759,8 +1759,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
                 bool *early_exit, bool *ignore_debugger)
 {
         int ret;
-        bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode ==
-                        NVGPU_COMPUTE_PREEMPTION_MODE_CILP) ;
+        bool cilp_enabled = false;
         u32 global_mask = 0, dbgr_control0, global_esr_copy;
         u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
         u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
@@ -1769,6 +1768,10 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
         *early_exit = false;
         *ignore_debugger = false;
 
+        if (fault_ch)
+                cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode ==
+                        NVGPU_COMPUTE_PREEMPTION_MODE_CILP);
+
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n",
                         gpc, tpc, global_esr);