diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-11-09 18:12:41 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-17 19:29:41 -0500 |
commit | 9d04e970937657d11620d812c29a5d10828440fc (patch) | |
tree | 78d06a0773317241ddfdc9d2b1bc6c871f3175c7 /drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |
parent | 35ae4194a05d47aa6d79353428f81f2ca47ce90f (diff) |
gpu: nvgpu: Remove separation of t18x code
Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.
Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 124 |
1 files changed, 62 insertions, 62 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 6ff1522b..f0b77ebd 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -180,7 +180,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
180 | lrf_ecc_ded_status, | 180 | lrf_ecc_ded_status, |
181 | &lrf_single_count_delta, | 181 | &lrf_single_count_delta, |
182 | lrf_double_count_delta); | 182 | lrf_double_count_delta); |
183 | g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] += | 183 | g->ecc.gr.sm_lrf_single_err_count.counters[tpc] += |
184 | lrf_single_count_delta; | 184 | lrf_single_count_delta; |
185 | } | 185 | } |
186 | if (lrf_ecc_ded_status) { | 186 | if (lrf_ecc_ded_status) { |
@@ -192,7 +192,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
192 | lrf_ecc_ded_status, | 192 | lrf_ecc_ded_status, |
193 | &lrf_double_count_delta, | 193 | &lrf_double_count_delta, |
194 | lrf_single_count_delta); | 194 | lrf_single_count_delta); |
195 | g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] += | 195 | g->ecc.gr.sm_lrf_double_err_count.counters[tpc] += |
196 | lrf_double_count_delta; | 196 | lrf_double_count_delta; |
197 | } | 197 | } |
198 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | 198 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, |
@@ -217,9 +217,9 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
217 | ecc_stats_reg_val = | 217 | ecc_stats_reg_val = |
218 | gk20a_readl(g, | 218 | gk20a_readl(g, |
219 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 219 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
220 | g->ecc.gr.t18x.sm_shm_sec_count.counters[tpc] += | 220 | g->ecc.gr.sm_shm_sec_count.counters[tpc] += |
221 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); | 221 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); |
222 | g->ecc.gr.t18x.sm_shm_sed_count.counters[tpc] += | 222 | g->ecc.gr.sm_shm_sed_count.counters[tpc] += |
223 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); | 223 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); |
224 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | | 224 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | |
225 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); | 225 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); |
@@ -239,7 +239,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
239 | ecc_stats_reg_val = | 239 | ecc_stats_reg_val = |
240 | gk20a_readl(g, | 240 | gk20a_readl(g, |
241 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 241 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
242 | g->ecc.gr.t18x.sm_shm_ded_count.counters[tpc] += | 242 | g->ecc.gr.sm_shm_ded_count.counters[tpc] += |
243 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); | 243 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); |
244 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); | 244 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); |
245 | gk20a_writel(g, | 245 | gk20a_writel(g, |
@@ -280,7 +280,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
280 | 280 | ||
281 | ecc_stats_reg_val = gk20a_readl(g, | 281 | ecc_stats_reg_val = gk20a_readl(g, |
282 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 282 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
283 | g->ecc.gr.t18x.tex_total_sec_pipe0_count.counters[tpc] += | 283 | g->ecc.gr.tex_total_sec_pipe0_count.counters[tpc] += |
284 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 284 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
285 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 285 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
286 | gk20a_writel(g, | 286 | gk20a_writel(g, |
@@ -289,7 +289,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
289 | 289 | ||
290 | ecc_stats_reg_val = gk20a_readl(g, | 290 | ecc_stats_reg_val = gk20a_readl(g, |
291 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 291 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
292 | g->ecc.gr.t18x.tex_unique_sec_pipe0_count.counters[tpc] += | 292 | g->ecc.gr.tex_unique_sec_pipe0_count.counters[tpc] += |
293 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 293 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
294 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 294 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
295 | gk20a_writel(g, | 295 | gk20a_writel(g, |
@@ -304,7 +304,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
304 | 304 | ||
305 | ecc_stats_reg_val = gk20a_readl(g, | 305 | ecc_stats_reg_val = gk20a_readl(g, |
306 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 306 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
307 | g->ecc.gr.t18x.tex_total_sec_pipe1_count.counters[tpc] += | 307 | g->ecc.gr.tex_total_sec_pipe1_count.counters[tpc] += |
308 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 308 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
309 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 309 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
310 | gk20a_writel(g, | 310 | gk20a_writel(g, |
@@ -313,7 +313,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
313 | 313 | ||
314 | ecc_stats_reg_val = gk20a_readl(g, | 314 | ecc_stats_reg_val = gk20a_readl(g, |
315 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 315 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
316 | g->ecc.gr.t18x.tex_unique_sec_pipe1_count.counters[tpc] += | 316 | g->ecc.gr.tex_unique_sec_pipe1_count.counters[tpc] += |
317 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 317 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
318 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 318 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
319 | gk20a_writel(g, | 319 | gk20a_writel(g, |
@@ -336,7 +336,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
336 | 336 | ||
337 | ecc_stats_reg_val = gk20a_readl(g, | 337 | ecc_stats_reg_val = gk20a_readl(g, |
338 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 338 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
339 | g->ecc.gr.t18x.tex_total_ded_pipe0_count.counters[tpc] += | 339 | g->ecc.gr.tex_total_ded_pipe0_count.counters[tpc] += |
340 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 340 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
341 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 341 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
342 | gk20a_writel(g, | 342 | gk20a_writel(g, |
@@ -345,7 +345,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
345 | 345 | ||
346 | ecc_stats_reg_val = gk20a_readl(g, | 346 | ecc_stats_reg_val = gk20a_readl(g, |
347 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 347 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
348 | g->ecc.gr.t18x.tex_unique_ded_pipe0_count.counters[tpc] += | 348 | g->ecc.gr.tex_unique_ded_pipe0_count.counters[tpc] += |
349 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 349 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
350 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 350 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
351 | gk20a_writel(g, | 351 | gk20a_writel(g, |
@@ -360,7 +360,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
360 | 360 | ||
361 | ecc_stats_reg_val = gk20a_readl(g, | 361 | ecc_stats_reg_val = gk20a_readl(g, |
362 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 362 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
363 | g->ecc.gr.t18x.tex_total_ded_pipe1_count.counters[tpc] += | 363 | g->ecc.gr.tex_total_ded_pipe1_count.counters[tpc] += |
364 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 364 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
365 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 365 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
366 | gk20a_writel(g, | 366 | gk20a_writel(g, |
@@ -369,7 +369,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
369 | 369 | ||
370 | ecc_stats_reg_val = gk20a_readl(g, | 370 | ecc_stats_reg_val = gk20a_readl(g, |
371 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 371 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
372 | g->ecc.gr.t18x.tex_unique_ded_pipe1_count.counters[tpc] += | 372 | g->ecc.gr.tex_unique_ded_pipe1_count.counters[tpc] += |
373 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 373 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
374 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 374 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
375 | gk20a_writel(g, | 375 | gk20a_writel(g, |
@@ -881,10 +881,10 @@ int gr_gp10b_init_ctx_state(struct gk20a *g) | |||
881 | if (err) | 881 | if (err) |
882 | return err; | 882 | return err; |
883 | 883 | ||
884 | if (!g->gr.t18x.ctx_vars.preempt_image_size) { | 884 | if (!g->gr.ctx_vars.preempt_image_size) { |
885 | op.method.addr = | 885 | op.method.addr = |
886 | gr_fecs_method_push_adr_discover_preemption_image_size_v(); | 886 | gr_fecs_method_push_adr_discover_preemption_image_size_v(); |
887 | op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; | 887 | op.mailbox.ret = &g->gr.ctx_vars.preempt_image_size; |
888 | err = gr_gk20a_submit_fecs_method_op(g, op, false); | 888 | err = gr_gk20a_submit_fecs_method_op(g, op, false); |
889 | if (err) { | 889 | if (err) { |
890 | nvgpu_err(g, "query preempt image size failed"); | 890 | nvgpu_err(g, "query preempt image size failed"); |
@@ -893,7 +893,7 @@ int gr_gp10b_init_ctx_state(struct gk20a *g) | |||
893 | } | 893 | } |
894 | 894 | ||
895 | gk20a_dbg_info("preempt image size: %u", | 895 | gk20a_dbg_info("preempt image size: %u", |
896 | g->gr.t18x.ctx_vars.preempt_image_size); | 896 | g->gr.ctx_vars.preempt_image_size); |
897 | 897 | ||
898 | gk20a_dbg_fn("done"); | 898 | gk20a_dbg_fn("done"); |
899 | 899 | ||
@@ -940,11 +940,11 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
940 | int err = 0; | 940 | int err = 0; |
941 | 941 | ||
942 | if (g->ops.gr.is_valid_gfx_class(g, class) && | 942 | if (g->ops.gr.is_valid_gfx_class(g, class) && |
943 | g->gr.t18x.ctx_vars.force_preemption_gfxp) | 943 | g->gr.ctx_vars.force_preemption_gfxp) |
944 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 944 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
945 | 945 | ||
946 | if (g->ops.gr.is_valid_compute_class(g, class) && | 946 | if (g->ops.gr.is_valid_compute_class(g, class) && |
947 | g->gr.t18x.ctx_vars.force_preemption_cilp) | 947 | g->gr.ctx_vars.force_preemption_cilp) |
948 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | 948 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; |
949 | 949 | ||
950 | /* check for invalid combinations */ | 950 | /* check for invalid combinations */ |
@@ -987,8 +987,8 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
987 | attrib_cb_size); | 987 | attrib_cb_size); |
988 | 988 | ||
989 | err = gr_gp10b_alloc_buffer(vm, | 989 | err = gr_gp10b_alloc_buffer(vm, |
990 | g->gr.t18x.ctx_vars.preempt_image_size, | 990 | g->gr.ctx_vars.preempt_image_size, |
991 | &gr_ctx->t18x.preempt_ctxsw_buffer); | 991 | &gr_ctx->preempt_ctxsw_buffer); |
992 | if (err) { | 992 | if (err) { |
993 | nvgpu_err(g, "cannot allocate preempt buffer"); | 993 | nvgpu_err(g, "cannot allocate preempt buffer"); |
994 | goto fail; | 994 | goto fail; |
@@ -996,7 +996,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
996 | 996 | ||
997 | err = gr_gp10b_alloc_buffer(vm, | 997 | err = gr_gp10b_alloc_buffer(vm, |
998 | spill_size, | 998 | spill_size, |
999 | &gr_ctx->t18x.spill_ctxsw_buffer); | 999 | &gr_ctx->spill_ctxsw_buffer); |
1000 | if (err) { | 1000 | if (err) { |
1001 | nvgpu_err(g, "cannot allocate spill buffer"); | 1001 | nvgpu_err(g, "cannot allocate spill buffer"); |
1002 | goto fail_free_preempt; | 1002 | goto fail_free_preempt; |
@@ -1004,7 +1004,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
1004 | 1004 | ||
1005 | err = gr_gp10b_alloc_buffer(vm, | 1005 | err = gr_gp10b_alloc_buffer(vm, |
1006 | attrib_cb_size, | 1006 | attrib_cb_size, |
1007 | &gr_ctx->t18x.betacb_ctxsw_buffer); | 1007 | &gr_ctx->betacb_ctxsw_buffer); |
1008 | if (err) { | 1008 | if (err) { |
1009 | nvgpu_err(g, "cannot allocate beta buffer"); | 1009 | nvgpu_err(g, "cannot allocate beta buffer"); |
1010 | goto fail_free_spill; | 1010 | goto fail_free_spill; |
@@ -1012,7 +1012,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
1012 | 1012 | ||
1013 | err = gr_gp10b_alloc_buffer(vm, | 1013 | err = gr_gp10b_alloc_buffer(vm, |
1014 | pagepool_size, | 1014 | pagepool_size, |
1015 | &gr_ctx->t18x.pagepool_ctxsw_buffer); | 1015 | &gr_ctx->pagepool_ctxsw_buffer); |
1016 | if (err) { | 1016 | if (err) { |
1017 | nvgpu_err(g, "cannot allocate page pool"); | 1017 | nvgpu_err(g, "cannot allocate page pool"); |
1018 | goto fail_free_betacb; | 1018 | goto fail_free_betacb; |
@@ -1046,11 +1046,11 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
1046 | return 0; | 1046 | return 0; |
1047 | 1047 | ||
1048 | fail_free_betacb: | 1048 | fail_free_betacb: |
1049 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | 1049 | nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer); |
1050 | fail_free_spill: | 1050 | fail_free_spill: |
1051 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | 1051 | nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer); |
1052 | fail_free_preempt: | 1052 | fail_free_preempt: |
1053 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | 1053 | nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer); |
1054 | fail: | 1054 | fail: |
1055 | return err; | 1055 | return err; |
1056 | } | 1056 | } |
@@ -1070,7 +1070,7 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g, | |||
1070 | if (err) | 1070 | if (err) |
1071 | return err; | 1071 | return err; |
1072 | 1072 | ||
1073 | (*gr_ctx)->t18x.ctx_id_valid = false; | 1073 | (*gr_ctx)->ctx_id_valid = false; |
1074 | 1074 | ||
1075 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) | 1075 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) |
1076 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 1076 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
@@ -1160,13 +1160,13 @@ void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | |||
1160 | if (!gr_ctx) | 1160 | if (!gr_ctx) |
1161 | return; | 1161 | return; |
1162 | 1162 | ||
1163 | if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close) | 1163 | if (g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close) |
1164 | dump_ctx_switch_stats(g, vm, gr_ctx); | 1164 | dump_ctx_switch_stats(g, vm, gr_ctx); |
1165 | 1165 | ||
1166 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); | 1166 | nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer); |
1167 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | 1167 | nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer); |
1168 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | 1168 | nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer); |
1169 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | 1169 | nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer); |
1170 | gr_gk20a_free_gr_ctx(g, vm, gr_ctx); | 1170 | gr_gk20a_free_gr_ctx(g, vm, gr_ctx); |
1171 | gk20a_dbg_fn("done"); | 1171 | gk20a_dbg_fn("done"); |
1172 | } | 1172 | } |
@@ -1211,7 +1211,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1211 | cta_preempt_option); | 1211 | cta_preempt_option); |
1212 | } | 1212 | } |
1213 | 1213 | ||
1214 | if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) { | 1214 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) { |
1215 | u32 addr; | 1215 | u32 addr; |
1216 | u32 size; | 1216 | u32 size; |
1217 | u32 cbes_reserve; | 1217 | u32 cbes_reserve; |
@@ -1219,10 +1219,10 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1219 | if (g->ops.gr.set_preemption_buffer_va) { | 1219 | if (g->ops.gr.set_preemption_buffer_va) { |
1220 | if (ctxheader->gpu_va) | 1220 | if (ctxheader->gpu_va) |
1221 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, | 1221 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, |
1222 | gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va); | 1222 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1223 | else | 1223 | else |
1224 | g->ops.gr.set_preemption_buffer_va(g, mem, | 1224 | g->ops.gr.set_preemption_buffer_va(g, mem, |
1225 | gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va); | 1225 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1226 | } | 1226 | } |
1227 | 1227 | ||
1228 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true); | 1228 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true); |
@@ -1231,30 +1231,30 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1231 | goto out; | 1231 | goto out; |
1232 | } | 1232 | } |
1233 | 1233 | ||
1234 | addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >> | 1234 | addr = (u64_lo32(gr_ctx->betacb_ctxsw_buffer.gpu_va) >> |
1235 | gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | | 1235 | gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | |
1236 | (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) << | 1236 | (u64_hi32(gr_ctx->betacb_ctxsw_buffer.gpu_va) << |
1237 | (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); | 1237 | (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); |
1238 | 1238 | ||
1239 | gk20a_dbg_info("attrib cb addr : 0x%016x", addr); | 1239 | gk20a_dbg_info("attrib cb addr : 0x%016x", addr); |
1240 | g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); | 1240 | g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); |
1241 | 1241 | ||
1242 | addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >> | 1242 | addr = (u64_lo32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) >> |
1243 | gr_scc_pagepool_base_addr_39_8_align_bits_v()) | | 1243 | gr_scc_pagepool_base_addr_39_8_align_bits_v()) | |
1244 | (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << | 1244 | (u64_hi32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) << |
1245 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); | 1245 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); |
1246 | size = gr_ctx->t18x.pagepool_ctxsw_buffer.size; | 1246 | size = gr_ctx->pagepool_ctxsw_buffer.size; |
1247 | 1247 | ||
1248 | if (size == g->ops.gr.pagepool_default_size(g)) | 1248 | if (size == g->ops.gr.pagepool_default_size(g)) |
1249 | size = gr_scc_pagepool_total_pages_hwmax_v(); | 1249 | size = gr_scc_pagepool_total_pages_hwmax_v(); |
1250 | 1250 | ||
1251 | g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); | 1251 | g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); |
1252 | 1252 | ||
1253 | addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> | 1253 | addr = (u64_lo32(gr_ctx->spill_ctxsw_buffer.gpu_va) >> |
1254 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | | 1254 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | |
1255 | (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << | 1255 | (u64_hi32(gr_ctx->spill_ctxsw_buffer.gpu_va) << |
1256 | (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); | 1256 | (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); |
1257 | size = gr_ctx->t18x.spill_ctxsw_buffer.size / | 1257 | size = gr_ctx->spill_ctxsw_buffer.size / |
1258 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); | 1258 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); |
1259 | 1259 | ||
1260 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 1260 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
@@ -1489,8 +1489,8 @@ void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, | |||
1489 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; | 1489 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; |
1490 | int attrBufferSize; | 1490 | int attrBufferSize; |
1491 | 1491 | ||
1492 | if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) | 1492 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) |
1493 | attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size; | 1493 | attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; |
1494 | else | 1494 | else |
1495 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); | 1495 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); |
1496 | 1496 | ||
@@ -1606,10 +1606,10 @@ int gr_gp10b_init_fs_state(struct gk20a *g) | |||
1606 | gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); | 1606 | gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); |
1607 | gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); | 1607 | gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); |
1608 | 1608 | ||
1609 | if (g->gr.t18x.fecs_feature_override_ecc_val != 0) { | 1609 | if (g->gr.fecs_feature_override_ecc_val != 0) { |
1610 | gk20a_writel(g, | 1610 | gk20a_writel(g, |
1611 | gr_fecs_feature_override_ecc_r(), | 1611 | gr_fecs_feature_override_ecc_r(), |
1612 | g->gr.t18x.fecs_feature_override_ecc_val); | 1612 | g->gr.fecs_feature_override_ecc_val); |
1613 | } | 1613 | } |
1614 | 1614 | ||
1615 | return gr_gm20b_init_fs_state(g); | 1615 | return gr_gm20b_init_fs_state(g); |
@@ -1718,7 +1718,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1718 | if (!gr_ctx) | 1718 | if (!gr_ctx) |
1719 | return -EINVAL; | 1719 | return -EINVAL; |
1720 | 1720 | ||
1721 | if (gr_ctx->t18x.cilp_preempt_pending) { | 1721 | if (gr_ctx->cilp_preempt_pending) { |
1722 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1722 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1723 | "CILP is already pending for chid %d", | 1723 | "CILP is already pending for chid %d", |
1724 | fault_ch->chid); | 1724 | fault_ch->chid); |
@@ -1726,24 +1726,24 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1726 | } | 1726 | } |
1727 | 1727 | ||
1728 | /* get ctx_id from the ucode image */ | 1728 | /* get ctx_id from the ucode image */ |
1729 | if (!gr_ctx->t18x.ctx_id_valid) { | 1729 | if (!gr_ctx->ctx_id_valid) { |
1730 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1730 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1731 | "CILP: looking up ctx id"); | 1731 | "CILP: looking up ctx id"); |
1732 | ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id); | 1732 | ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->ctx_id); |
1733 | if (ret) { | 1733 | if (ret) { |
1734 | nvgpu_err(g, "CILP: error looking up ctx id!"); | 1734 | nvgpu_err(g, "CILP: error looking up ctx id!"); |
1735 | return ret; | 1735 | return ret; |
1736 | } | 1736 | } |
1737 | gr_ctx->t18x.ctx_id_valid = true; | 1737 | gr_ctx->ctx_id_valid = true; |
1738 | } | 1738 | } |
1739 | 1739 | ||
1740 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1740 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1741 | "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id); | 1741 | "CILP: ctx id is 0x%x", gr_ctx->ctx_id); |
1742 | 1742 | ||
1743 | /* send ucode method to set ctxsw interrupt */ | 1743 | /* send ucode method to set ctxsw interrupt */ |
1744 | ret = gr_gk20a_submit_fecs_sideband_method_op(g, | 1744 | ret = gr_gk20a_submit_fecs_sideband_method_op(g, |
1745 | (struct fecs_method_op_gk20a) { | 1745 | (struct fecs_method_op_gk20a) { |
1746 | .method.data = gr_ctx->t18x.ctx_id, | 1746 | .method.data = gr_ctx->ctx_id, |
1747 | .method.addr = | 1747 | .method.addr = |
1748 | gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), | 1748 | gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), |
1749 | .mailbox = { | 1749 | .mailbox = { |
@@ -1773,8 +1773,8 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1773 | } | 1773 | } |
1774 | 1774 | ||
1775 | /* set cilp_preempt_pending = true and record the channel */ | 1775 | /* set cilp_preempt_pending = true and record the channel */ |
1776 | gr_ctx->t18x.cilp_preempt_pending = true; | 1776 | gr_ctx->cilp_preempt_pending = true; |
1777 | g->gr.t18x.cilp_preempt_pending_chid = fault_ch->chid; | 1777 | g->gr.cilp_preempt_pending_chid = fault_ch->chid; |
1778 | 1778 | ||
1779 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { | 1779 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { |
1780 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; | 1780 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; |
@@ -1801,15 +1801,15 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, | |||
1801 | 1801 | ||
1802 | /* The ucode is self-clearing, so all we need to do here is | 1802 | /* The ucode is self-clearing, so all we need to do here is |
1803 | to clear cilp_preempt_pending. */ | 1803 | to clear cilp_preempt_pending. */ |
1804 | if (!gr_ctx->t18x.cilp_preempt_pending) { | 1804 | if (!gr_ctx->cilp_preempt_pending) { |
1805 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1805 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1806 | "CILP is already cleared for chid %d\n", | 1806 | "CILP is already cleared for chid %d\n", |
1807 | fault_ch->chid); | 1807 | fault_ch->chid); |
1808 | return 0; | 1808 | return 0; |
1809 | } | 1809 | } |
1810 | 1810 | ||
1811 | gr_ctx->t18x.cilp_preempt_pending = false; | 1811 | gr_ctx->cilp_preempt_pending = false; |
1812 | g->gr.t18x.cilp_preempt_pending_chid = -1; | 1812 | g->gr.cilp_preempt_pending_chid = -1; |
1813 | 1813 | ||
1814 | return 0; | 1814 | return 0; |
1815 | } | 1815 | } |
@@ -1925,7 +1925,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) | |||
1925 | int chid; | 1925 | int chid; |
1926 | int ret = -EINVAL; | 1926 | int ret = -EINVAL; |
1927 | 1927 | ||
1928 | chid = g->gr.t18x.cilp_preempt_pending_chid; | 1928 | chid = g->gr.cilp_preempt_pending_chid; |
1929 | 1929 | ||
1930 | ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); | 1930 | ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); |
1931 | if (!ch) | 1931 | if (!ch) |
@@ -1933,7 +1933,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) | |||
1933 | 1933 | ||
1934 | gr_ctx = ch->ch_ctx.gr_ctx; | 1934 | gr_ctx = ch->ch_ctx.gr_ctx; |
1935 | 1935 | ||
1936 | if (gr_ctx->t18x.cilp_preempt_pending) { | 1936 | if (gr_ctx->cilp_preempt_pending) { |
1937 | *__chid = chid; | 1937 | *__chid = chid; |
1938 | ret = 0; | 1938 | ret = 0; |
1939 | } | 1939 | } |
@@ -2121,7 +2121,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, | |||
2121 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), | 2121 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), |
2122 | NVGPU_TIMER_CPU_TIMER); | 2122 | NVGPU_TIMER_CPU_TIMER); |
2123 | do { | 2123 | do { |
2124 | if (!gr_ctx->t18x.cilp_preempt_pending) | 2124 | if (!gr_ctx->cilp_preempt_pending) |
2125 | break; | 2125 | break; |
2126 | 2126 | ||
2127 | nvgpu_usleep_range(delay, delay * 2); | 2127 | nvgpu_usleep_range(delay, delay * 2); |
@@ -2129,7 +2129,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, | |||
2129 | } while (!nvgpu_timeout_expired(&timeout)); | 2129 | } while (!nvgpu_timeout_expired(&timeout)); |
2130 | 2130 | ||
2131 | /* If cilp is still pending at this point, timeout */ | 2131 | /* If cilp is still pending at this point, timeout */ |
2132 | if (gr_ctx->t18x.cilp_preempt_pending) | 2132 | if (gr_ctx->cilp_preempt_pending) |
2133 | err = -ETIMEDOUT; | 2133 | err = -ETIMEDOUT; |
2134 | } | 2134 | } |
2135 | 2135 | ||