diff options
| author | Seema Khowala <seemaj@nvidia.com> | 2017-06-22 00:28:10 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-06 15:04:42 -0400 |
| commit | 9891cb117e538f1ea5d19171a3c88422cdce7162 (patch) | |
| tree | e03b1baecbcebd5f6eaeb80eba4cecfb6d2940aa /drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |
| parent | 64076b4b214b45fe8367e467dd6796a9bcc058a4 (diff) | |
gpu: nvgpu: add gr ops get_sm_hww_global_esr
Required for multiple SM support and t19x sm register
address changes
JIRA GPUT19X-75
Change-Id: I437095cb8f8d2ba31b85594a7609532991441a37
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514040
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
| -rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 64ec5e1a..27d609d1 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
| @@ -1833,7 +1833,8 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
| 1833 | } | 1833 | } |
| 1834 | 1834 | ||
| 1835 | /* reset the HWW errors after locking down */ | 1835 | /* reset the HWW errors after locking down */ |
| 1836 | global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | 1836 | global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, |
| 1837 | gpc, tpc, sm); | ||
| 1837 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); | 1838 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); |
| 1838 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1839 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
| 1839 | "CILP: HWWs cleared for gpc %d tpc %d\n", | 1840 | "CILP: HWWs cleared for gpc %d tpc %d\n", |