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authorSeema Khowala <seemaj@nvidia.com>2017-06-20 16:26:16 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-29 16:29:35 -0400
commit97aea977e25c17ecb44448eb19dc15e740036958 (patch)
tree5ac50bec7d1759adac13d91efb5ab6301462efb7 /drivers/gpu/nvgpu/gp10b/gr_gp10b.c
parent2fcec1c8d54e65d4ccfe66f5a094a01ac69926a0 (diff)
gpu: nvgpu: gp10b: functions made non-static
gr_gp10b_handle_fecs_error and gr_gp10b_set_cilp_preempt_pending made non-static to be reused for t19x Bug 200289491 Change-Id: I8ef7ffab1209abc7f7d7d05cbbdf8ce4365613c5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1505954 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c19
1 files changed, 13 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 64466936..384ca28d 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1645,17 +1645,24 @@ static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a
1645 1645
1646 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); 1646 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist");
1647 1647
1648 if (gk20a_is_channel_marked_as_tsg(fault_ch)) 1648 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1649 "CILP: tsgid: 0x%x", fault_ch->tsgid);
1650
1651 if (gk20a_is_channel_marked_as_tsg(fault_ch)) {
1649 gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); 1652 gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true);
1650 else 1653 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1654 "CILP: preempted tsg");
1655 } else {
1651 gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false); 1656 gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false);
1652 1657 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1653 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted the channel/tsg"); 1658 "CILP: preempted channel");
1659 }
1654 1660
1655 return ret; 1661 return ret;
1656} 1662}
1657 1663
1658static int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch) 1664int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
1665 struct channel_gk20a *fault_ch)
1659{ 1666{
1660 int ret; 1667 int ret;
1661 struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; 1668 struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx;
@@ -1888,7 +1895,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid)
1888 return ret; 1895 return ret;
1889} 1896}
1890 1897
1891static int gr_gp10b_handle_fecs_error(struct gk20a *g, 1898int gr_gp10b_handle_fecs_error(struct gk20a *g,
1892 struct channel_gk20a *__ch, 1899 struct channel_gk20a *__ch,
1893 struct gr_gk20a_isr_data *isr_data) 1900 struct gr_gk20a_isr_data *isr_data)
1894{ 1901{