gpu: nvgpu: gp10b: Set address check mode

Set address check mode for SM.

Bug 1625763

Change-Id: I5ddf8334673b414956e57c55aaa5be1a9f9aeaf1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752139

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 045847b2..265cad66 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -905,12 +905,24 @@ static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
         gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(),
                 gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) |
                 gr_pd_ab_dist_cfg2_state_limit_f(data), patch);
+}
+
+static int gr_gp10b_init_fs_state(struct gk20a *g)
+{
+        u32 data;
+
+        data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r());
+        data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(),
+                        gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
+        gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
 
+        return gr_gm20b_ctx_state_floorsweep(g);
 }
 
 void gp10b_init_gr(struct gpu_ops *gops)
 {
         gm20b_init_gr(gops);
+        gops->gr.init_fs_state = gr_gp10b_init_fs_state;
         gops->gr.is_valid_class = gr_gp10b_is_valid_class;
         gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager;
         gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool;