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authorDeepak Nibade <dnibade@nvidia.com>2016-12-13 03:41:24 -0500
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:52 -0500
commit8f8ee32cd6082b8eee9585e9334656d1365c5273 (patch)
treeea59b89994f0a75779274808b1c02bbd5b742244 /drivers/gpu/nvgpu/gp10b/gr_gp10b.c
parent1710bdb0783a85ce183a77d182fb18d7f98af66e (diff)
gpu: nvgpu: use common API to write TPC fuses
Use common fuse write API tegra_fuse_control_write which should work on all kernel versions Bug 200262155 Change-Id: I29e8514e9660549ecf94711287ec4bbf4c897a86 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1270169 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c11
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index aa2e3b65..91ea086c 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1543,20 +1543,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g)
1543 1543
1544static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) 1544static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1545{ 1545{
1546#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
1547 tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0);
1548 tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0);
1549#else
1550 tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); 1546 tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0);
1551 tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); 1547 tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0);
1552#endif
1553 1548
1554 if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) 1549 if (g->gr.gpc_tpc_mask[gpc_index] == 0x1)
1555 tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); 1550 tegra_fuse_control_write(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0);
1556 else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) 1551 else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2)
1557 tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); 1552 tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
1558 else 1553 else
1559 tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); 1554 tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
1560} 1555}
1561 1556
1562static void gr_gp10b_get_access_map(struct gk20a *g, 1557static void gr_gp10b_get_access_map(struct gk20a *g,