gpu: nvgpu: Implement get_rate/set_rate as GPU op

Move clock APIs from gk20a_platform to gpu_ops. At the same time
allow use of internal get_rate/set_rate for querying both GPCCLK
and PWRCLK on iGPU.

At the same time we can replace calls to clk framework with the
new HAL and drop direct dependency to clk framework.

gp10b ops were replaced as a whole at HAL initialization. That
replaces anything set in platform probe stage, so reduce that to
touch only clock gating regs.

Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1300113
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 96919d2e..c4d097a7 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -13,7 +13,6 @@
  * more details.
  */
 
-#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/version.h>
 #include <linux/vmalloc.h>
@@ -2255,12 +2254,11 @@ static int gp10b_gr_fuse_override(struct gk20a *g)
 
 static int gr_gp10b_init_preemption_state(struct gk20a *g)
 {
-        struct gk20a_platform *platform = gk20a_get_platform(g->dev);
         u32 debug_2;
         u64 sysclk_rate;
         u32 sysclk_cycles;
 
-        sysclk_rate = platform->clk_get_rate(g->dev);
+        sysclk_rate = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPCCLK);
         sysclk_cycles = (u32)((sysclk_rate * NVGPU_GFXP_WFI_TIMEOUT_US) / 1000000ULL);
         gk20a_writel(g, gr_fe_gfxp_wfi_timeout_r(),
                         gr_fe_gfxp_wfi_timeout_count_f(sysclk_cycles));