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authorSeema Khowala <seemaj@nvidia.com>2017-06-21 00:50:36 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-29 16:28:54 -0400
commit2eea080584b36747d7f8a7d5120d60be25d12242 (patch)
treeee3e9c817ce917c0daf4352d563334aaa096e003 /drivers/gpu/nvgpu/gp10b/gr_gp10b.c
parent02d1e7ae979eedf74a27f0ec57bde85c06ba2d35 (diff)
gpu: nvgpu: Support multiple SM for t19x
-Add sm input param for handle_sm_exception and pre_process_sm_exception for gr ops/functions. -Add functions to calculate gpc and tpc reg offsets. -Add function to find SMs which raised SM exception. JIRA GPUT19X-75 Change-Id: I257e7342ddabadb1556c9551c50a54d34b0f9d1e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1476108 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index f27e2605..64466936 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -118,7 +118,8 @@ static void gr_gp10b_sm_lrf_ecc_overcount_war(int single_err,
118 *count_to_adjust = 0; 118 *count_to_adjust = 0;
119} 119}
120 120
121static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, 121static int gr_gp10b_handle_sm_exception(struct gk20a *g,
122 u32 gpc, u32 tpc, u32 sm,
122 bool *post_event, struct channel_gk20a *fault_ch, 123 bool *post_event, struct channel_gk20a *fault_ch,
123 u32 *hww_global_esr) 124 u32 *hww_global_esr)
124{ 125{
@@ -130,7 +131,8 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
130 u32 lrf_single_count_delta, lrf_double_count_delta; 131 u32 lrf_single_count_delta, lrf_double_count_delta;
131 u32 shm_ecc_status; 132 u32 shm_ecc_status;
132 133
133 gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); 134 gr_gk20a_handle_sm_exception(g,
135 gpc, tpc, sm, post_event, fault_ch, hww_global_esr);
134 136
135 /* Check for LRF ECC errors. */ 137 /* Check for LRF ECC errors. */
136 lrf_ecc_status = gk20a_readl(g, 138 lrf_ecc_status = gk20a_readl(g,
@@ -1764,7 +1766,7 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g,
1764 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing 1766 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing
1765 */ 1767 */
1766static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, 1768static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
1767 u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, 1769 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
1768 bool sm_debugger_attached, struct channel_gk20a *fault_ch, 1770 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
1769 bool *early_exit, bool *ignore_debugger) 1771 bool *early_exit, bool *ignore_debugger)
1770{ 1772{