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authorAlex Waterman <alexw@nvidia.com>2018-01-08 20:57:02 -0500
committerTimo Alho <talho@nvidia.com>2018-01-09 09:32:30 -0500
commit2ae16008cdfd778bc981cea4d5a90fb988f0850b (patch)
treee91e67d6b8acd3be015a8fe18961e658f5408abd /drivers/gpu/nvgpu/gp10b/gr_gp10b.c
parent7703ac33f488bb2a18f17a51c8748874adda1256 (diff)
Revert "gpu: nvgpu: gv11b: fix for gfx preemption"
This reverts commit caf168e33ec12ff6f0ed90fd4aa7654c09eaa553. Might be causing an intermittency in quill-c03 graphics submit. Super weird since the only change that seems like it could affect it is the header file update but that seems rather safe. Bug 2044830 Change-Id: I14809d4945744193b9c2d7729ae8a516eb3e0b21 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1634349 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 942ebf24..b5194223 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B GPU GR 2 * GP10B GPU GR
3 * 3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -406,8 +406,12 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
406 gk20a_dbg_fn(""); 406 gk20a_dbg_fn("");
407 407
408 if (gr_ctx->graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) { 408 if (gr_ctx->graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) {
409 attrib_size_in_chunk = gr->attrib_cb_gfxp_size; 409 attrib_size_in_chunk = gr->attrib_cb_default_size +
410 cb_attrib_cache_size_init = gr->attrib_cb_gfxp_default_size; 410 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
411 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
412 cb_attrib_cache_size_init = gr->attrib_cb_default_size +
413 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
414 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
411 } else { 415 } else {
412 attrib_size_in_chunk = gr->attrib_cb_size; 416 attrib_size_in_chunk = gr->attrib_cb_size;
413 cb_attrib_cache_size_init = gr->attrib_cb_default_size; 417 cb_attrib_cache_size_init = gr->attrib_cb_default_size;
@@ -734,10 +738,6 @@ void gr_gp10b_cb_size_default(struct gk20a *g)
734 gr->attrib_cb_default_size = 0x800; 738 gr->attrib_cb_default_size = 0x800;
735 gr->alpha_cb_default_size = 739 gr->alpha_cb_default_size =
736 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 740 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
737 gr->attrib_cb_gfxp_default_size =
738 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
739 gr->attrib_cb_gfxp_size =
740 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
741} 741}
742 742
743void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) 743void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)