gpu: nvgpu: gp10b specific CB callbacks

Bug 1570662

Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592101
GVS: Gerrit_Virtual_Submit

1 files changed, 114 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index f4a63fad..b7a52be0 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -19,7 +19,8 @@
 
 #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
 #include "gp10b/gr_gp10b.h"
-
+#include "hw_gr_gp10b.h"
+#include "hw_proj_gp10b.h"
 
 bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
 {
@@ -47,8 +48,120 @@ bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
         return valid;
 }
 
+int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
+                        struct channel_gk20a *c, bool patch)
+{
+        struct gr_gk20a *gr = &g->gr;
+        struct channel_ctx_gk20a *ch_ctx = NULL;
+        u32 attrib_offset_in_chunk = 0;
+        u32 alpha_offset_in_chunk = 0;
+        u32 pd_ab_max_output;
+        u32 gpc_index, ppc_index;
+        u32 temp;
+        u32 cbm_cfg_size1, cbm_cfg_size2;
+
+        gk20a_dbg_fn("");
+
+        if (patch) {
+                int err;
+                ch_ctx = &c->ch_ctx;
+                err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
+                if (err)
+                        return err;
+        }
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(),
+                gr->attrib_cb_default_size, patch);
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(),
+                gr->alpha_cb_default_size, patch);
+
+        pd_ab_max_output = (gr->alpha_cb_default_size *
+                gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) /
+                gr_pd_ab_dist_cfg1_max_output_granularity_v();
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(),
+                gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) |
+                gr_pd_ab_dist_cfg1_max_batches_init_f(), patch);
+
+        alpha_offset_in_chunk = attrib_offset_in_chunk +
+                gr->tpc_count * gr->attrib_cb_size;
+
+        for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
+                temp = proj_gpc_stride_v() * gpc_index;
+                for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
+                     ppc_index++) {
+                        cbm_cfg_size1 = gr->attrib_cb_default_size *
+                                gr->pes_tpc_count[ppc_index][gpc_index];
+                        cbm_cfg_size2 = gr->alpha_cb_default_size *
+                                gr->pes_tpc_count[ppc_index][gpc_index];
+
+                        gr_gk20a_ctx_patch_write(g, ch_ctx,
+                                gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp +
+                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                cbm_cfg_size1, patch);
+
+                        gr_gk20a_ctx_patch_write(g, ch_ctx,
+                                gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp +
+                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                attrib_offset_in_chunk, patch);
+
+                        attrib_offset_in_chunk += gr->attrib_cb_size *
+                                gr->pes_tpc_count[ppc_index][gpc_index];
+
+                        gr_gk20a_ctx_patch_write(g, ch_ctx,
+                                gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp +
+                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                cbm_cfg_size2, patch);
+
+                        gr_gk20a_ctx_patch_write(g, ch_ctx,
+                                gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp +
+                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                alpha_offset_in_chunk, patch);
+
+                        alpha_offset_in_chunk += gr->alpha_cb_size *
+                                gr->pes_tpc_count[ppc_index][gpc_index];
+
+                        gr_gk20a_ctx_patch_write(g, ch_ctx,
+                                gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp +
+                                proj_ppc_in_gpc_stride_v() * ppc_index,
+                                gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index],
+                                patch);
+
+                        gr_gk20a_ctx_patch_write(g, ch_ctx,
+                                gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + gpc_index),
+                                gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size1),
+                                patch);
+                }
+        }
+
+        if (patch)
+                gr_gk20a_ctx_patch_write_end(g, ch_ctx);
+
+        return 0;
+}
+
+void gr_gp10b_commit_global_pagepool(struct gk20a *g,
+                                            struct channel_ctx_gk20a *ch_ctx,
+                                            u64 addr, u32 size, bool patch)
+{
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(),
+                gr_scc_pagepool_base_addr_39_8_f(addr), patch);
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(),
+                gr_scc_pagepool_total_pages_f(size) |
+                gr_scc_pagepool_valid_true_f(), patch);
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(),
+                gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch);
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(),
+                gr_gpcs_gcc_pagepool_total_pages_f(size), patch);
+}
+
 void gp10b_init_gr(struct gpu_ops *gops)
 {
         gm20b_init_gr(gops);
         gops->gr.is_valid_class = gr_gp10b_is_valid_class;
+        gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager;
+        gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool;
 }