gpu: nvgpu: gp10b: Add tile caching registers

Add tile caching registers to access map.

Bug 1692373

Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 9c83030f..45befc51 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1072,7 +1072,31 @@ static void gr_gp10b_get_access_map(struct gk20a *g,
         static u32 wl_addr_gp10b[] = {
                 /* this list must be sorted (low to high) */
                 0x404468, /* gr_pri_mme_max_instructions       */
+                0x418300, /* gr_pri_gpcs_rasterarb_line_class  */
                 0x418800, /* gr_pri_gpcs_setup_debug           */
+                0x418e00, /* gr_pri_gpcs_swdx_config           */
+                0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl   */
+                0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr   */
+                0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */
                 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg      */
                 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg     */
                 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */