diff options
author | Vinod G <vinodg@nvidia.com> | 2018-07-10 19:13:03 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-19 03:06:43 -0400 |
commit | d859c5f4a03b975dc493f72a35016e83adad279a (patch) | |
tree | e7a1242a1d130a726456cf3a928a34941aad98f4 /drivers/gpu/nvgpu/gp10b/gp10b.c | |
parent | 74e1a11d840b3d7411b380c2e4e4c99126ea32a5 (diff) |
nvgpu: gv11b: Rearrange gr function
Moved gv11b_detect_ecc_enabled_units function
from gv11b.c to gr_gv11b.c, as this is being
used only in gr_gv11b file.
In order to avoid GR code touching fuse registers,
as it need to include fuse HW headers in GR code,
introduced two fuse HALs which are being called
from GR code. is_opt_ecc_enable for checking
whether ecc enable bit is set in fuse register
and is_opt_feature_overide_disable for checking
whether feature override disable bit is set in
fuse register.
Initialized fuse HAL functions for chips that
make use of those HAL functions.
JIRA NVGPU-615
Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775564
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c index 51dc4301..7991944c 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Graphics | 2 | * GP10B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,15 +28,13 @@ | |||
28 | 28 | ||
29 | #include "gp10b.h" | 29 | #include "gp10b.h" |
30 | 30 | ||
31 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
32 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | 31 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> |
33 | 32 | ||
34 | static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | 33 | static void gp10b_detect_ecc_enabled_units(struct gk20a *g) |
35 | { | 34 | { |
36 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); | 35 | bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g); |
37 | u32 opt_feature_fuses_override_disable = | 36 | bool opt_feature_fuses_override_disable = |
38 | gk20a_readl(g, | 37 | g->ops.fuse.is_opt_feature_override_disable(g); |
39 | fuse_opt_feature_fuses_override_disable_r()); | ||
40 | u32 fecs_feature_override_ecc = | 38 | u32 fecs_feature_override_ecc = |
41 | gk20a_readl(g, | 39 | gk20a_readl(g, |
42 | gr_fecs_feature_override_ecc_r()); | 40 | gr_fecs_feature_override_ecc_r()); |
@@ -51,9 +49,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
51 | } else { | 49 | } else { |
52 | /* SM LRF */ | 50 | /* SM LRF */ |
53 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | 51 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( |
54 | fecs_feature_override_ecc)) { | 52 | fecs_feature_override_ecc) == 1U) { |
55 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | 53 | if (gr_fecs_feature_override_ecc_sm_lrf_v( |
56 | fecs_feature_override_ecc)) { | 54 | fecs_feature_override_ecc) == 1U) { |
57 | __nvgpu_set_enabled(g, | 55 | __nvgpu_set_enabled(g, |
58 | NVGPU_ECC_ENABLED_SM_LRF, true); | 56 | NVGPU_ECC_ENABLED_SM_LRF, true); |
59 | } | 57 | } |
@@ -66,9 +64,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
66 | 64 | ||
67 | /* SM SHM */ | 65 | /* SM SHM */ |
68 | if (gr_fecs_feature_override_ecc_sm_shm_override_v( | 66 | if (gr_fecs_feature_override_ecc_sm_shm_override_v( |
69 | fecs_feature_override_ecc)) { | 67 | fecs_feature_override_ecc) == 1U) { |
70 | if (gr_fecs_feature_override_ecc_sm_shm_v( | 68 | if (gr_fecs_feature_override_ecc_sm_shm_v( |
71 | fecs_feature_override_ecc)) { | 69 | fecs_feature_override_ecc) == 1U) { |
72 | __nvgpu_set_enabled(g, | 70 | __nvgpu_set_enabled(g, |
73 | NVGPU_ECC_ENABLED_SM_SHM, true); | 71 | NVGPU_ECC_ENABLED_SM_SHM, true); |
74 | } | 72 | } |
@@ -81,9 +79,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
81 | 79 | ||
82 | /* TEX */ | 80 | /* TEX */ |
83 | if (gr_fecs_feature_override_ecc_tex_override_v( | 81 | if (gr_fecs_feature_override_ecc_tex_override_v( |
84 | fecs_feature_override_ecc)) { | 82 | fecs_feature_override_ecc) == 1U) { |
85 | if (gr_fecs_feature_override_ecc_tex_v( | 83 | if (gr_fecs_feature_override_ecc_tex_v( |
86 | fecs_feature_override_ecc)) { | 84 | fecs_feature_override_ecc) == 1U) { |
87 | __nvgpu_set_enabled(g, | 85 | __nvgpu_set_enabled(g, |
88 | NVGPU_ECC_ENABLED_TEX, true); | 86 | NVGPU_ECC_ENABLED_TEX, true); |
89 | } | 87 | } |
@@ -96,9 +94,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
96 | 94 | ||
97 | /* LTC */ | 95 | /* LTC */ |
98 | if (gr_fecs_feature_override_ecc_ltc_override_v( | 96 | if (gr_fecs_feature_override_ecc_ltc_override_v( |
99 | fecs_feature_override_ecc)) { | 97 | fecs_feature_override_ecc) == 1U) { |
100 | if (gr_fecs_feature_override_ecc_ltc_v( | 98 | if (gr_fecs_feature_override_ecc_ltc_v( |
101 | fecs_feature_override_ecc)) { | 99 | fecs_feature_override_ecc) == 1U) { |
102 | __nvgpu_set_enabled(g, | 100 | __nvgpu_set_enabled(g, |
103 | NVGPU_ECC_ENABLED_LTC, true); | 101 | NVGPU_ECC_ENABLED_LTC, true); |
104 | } | 102 | } |