diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-08-10 17:09:36 -0400 |
---|---|---|
committer | Bo Yan <byan@nvidia.com> | 2018-08-20 14:00:59 -0400 |
commit | 227c6f7b7a499dd58e0db6859736cfe586ef0897 (patch) | |
tree | d354f8422647021693aefefa5124d865c29ecd32 /drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | |
parent | 9e69e0cf978b53706f55ffb873e3966b4bb3a7a8 (diff) |
gpu: nvgpu: Move fuse HAL to common
Move implementation of fuse HAL to common/fuse. Also implements new
fuse query functions for FBIO, FBP, TPC floorsweeping and security
fuses.
JIRA NVGPU-957
Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797177
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fuse_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | 105 |
1 files changed, 0 insertions, 105 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c deleted file mode 100644 index a79d5e1c..00000000 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c +++ /dev/null | |||
@@ -1,105 +0,0 @@ | |||
1 | /* | ||
2 | * GP10B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/fuse.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | #include <nvgpu/io.h> | ||
29 | |||
30 | #include "gk20a/gk20a.h" | ||
31 | |||
32 | #include "gm20b/fuse_gm20b.h" | ||
33 | |||
34 | #include "fuse_gp10b.h" | ||
35 | |||
36 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
37 | |||
38 | int gp10b_fuse_check_priv_security(struct gk20a *g) | ||
39 | { | ||
40 | u32 gcplex_config; | ||
41 | |||
42 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
43 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
44 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
45 | nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel"); | ||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { | ||
50 | nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); | ||
51 | return -EINVAL; | ||
52 | } | ||
53 | |||
54 | if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { | ||
55 | /* | ||
56 | * all falcons have to boot in LS mode and this needs | ||
57 | * wpr_enabled set to 1 and vpr_auto_fetch_disable | ||
58 | * set to 0. In this case gmmu tries to pull wpr | ||
59 | * and vpr settings from tegra mc | ||
60 | */ | ||
61 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
62 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
63 | if ((gcplex_config & | ||
64 | GCPLEX_CONFIG_WPR_ENABLED_MASK) && | ||
65 | !(gcplex_config & | ||
66 | GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { | ||
67 | if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) | ||
68 | nvgpu_log(g, gpu_dbg_info, | ||
69 | "gcplex_config = 0x%08x, " | ||
70 | "secure mode: ACR debug", | ||
71 | gcplex_config); | ||
72 | else | ||
73 | nvgpu_log(g, gpu_dbg_info, | ||
74 | "gcplex_config = 0x%08x, " | ||
75 | "secure mode: ACR non debug", | ||
76 | gcplex_config); | ||
77 | |||
78 | } else { | ||
79 | nvgpu_err(g, "gcplex_config = 0x%08x " | ||
80 | "invalid wpr_enabled/vpr_auto_fetch_disable " | ||
81 | "with priv_sec_en", gcplex_config); | ||
82 | /* do not try to boot GPU */ | ||
83 | return -EINVAL; | ||
84 | } | ||
85 | } else { | ||
86 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
87 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
88 | nvgpu_log(g, gpu_dbg_info, | ||
89 | "gcplex_config = 0x%08x, non secure mode", | ||
90 | gcplex_config); | ||
91 | } | ||
92 | |||
93 | return 0; | ||
94 | } | ||
95 | |||
96 | bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g) | ||
97 | { | ||
98 | return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U; | ||
99 | } | ||
100 | |||
101 | bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g) | ||
102 | { | ||
103 | return gk20a_readl(g, | ||
104 | fuse_opt_feature_fuses_override_disable_r()) != 0U; | ||
105 | } | ||