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authorSunny He <suhe@nvidia.com>2017-06-30 18:53:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-24 02:35:06 -0400
commit66ec347db401affd8bcd425dc123e7162b9ae3bb (patch)
treecbeb24e465208c6ab3b9527a86ba35003837f176 /drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
parent2b582c5141752ff272c5d059b56433155bc3985a (diff)
gpu: nvgpu: Reorg fifo HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522553 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.h')
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.h17
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
index da0e82a9..369bed9a 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B Fifo 2 * GP10B Fifo
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -18,8 +18,21 @@
18 18
19struct gpu_ops; 19struct gpu_ops;
20struct channel_gk20a; 20struct channel_gk20a;
21struct fifo_gk20a;
22struct mmu_fault_info;
21 23
22void gp10b_init_fifo(struct gpu_ops *gops); 24int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
25 u64 gpfifo_base, u32 gpfifo_entries,
26 unsigned long acquire_timeout, u32 flags);
27u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g);
28int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c);
29int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
30 u32 *inst_id);
31void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
32 u32 *inst_id, u32 *pri_base, u32 *fault_id);
33void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
34void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
35 struct mmu_fault_info *mmfault);
23int channel_gp10b_commit_userd(struct channel_gk20a *c); 36int channel_gp10b_commit_userd(struct channel_gk20a *c);
24 37
25#endif 38#endif