gpu: nvgpu: Disable channel when writing syncpt id

Kick channel off PBDMA before writing new sync point id to allowed
sync points.

Bug 1648297
Bug 1646477

Change-Id: I7c686d474c403fdd54bc64cff63b7d049feecb4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/750981

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index d62f7316..3a6c3c23 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -156,6 +156,13 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
         gk20a_dbg_fn("");
 
         inst_ptr = c->inst_block.cpu_va;
+
+        /* disable channel */
+        c->g->ops.fifo.disable_channel(c);
+
+        /* preempt the channel */
+        WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid));
+
         if (c->sync) {
                 u32 v = pbdma_allowed_syncpoints_0_valid_f(1);
 
@@ -166,8 +173,15 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
                 v |= pbdma_allowed_syncpoints_0_index_f(syncpt_id);
 
                 gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), v);
+        } else {
+                gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), 0);
         }
 
+        /* enable channel */
+        gk20a_writel(c->g, ccsr_channel_r(c->hw_chid),
+                gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
+                ccsr_channel_enable_set_true_f());
+
         gk20a_dbg_fn("done");
 
         return 0;