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authorLakshmanan M <lm@nvidia.com>2016-06-02 00:09:52 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:17 -0500
commit9454529abe0ac42d15df01e36898cd2c840de9c8 (patch)
tree6d965a08f74b72aa948edcb224a4f753d86f3b90 /drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
parentc8569f1ebfcdd4546d3674458684c7e1315872a4 (diff)
gpu: nvgpu: Add multiple engine and runlist support
This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index aa38dc54..0aa6e29e 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -188,15 +188,17 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
188 gk20a_dbg_info("engine type %d", engine_type); 188 gk20a_dbg_info("engine type %d", engine_type);
189 if (engine_type == top_device_info_type_enum_graphics_v()) 189 if (engine_type == top_device_info_type_enum_graphics_v())
190 ret = ENGINE_GR_GK20A; 190 ret = ENGINE_GR_GK20A;
191 else if (engine_type == top_device_info_type_enum_lce_v()) 191 else if (engine_type == top_device_info_type_enum_lce_v()) {
192 ret = ENGINE_CE2_GK20A; 192 /* Default assumptions - all the CE engine have separate runlist */
193 ret = ENGINE_ASYNC_CE_GK20A;
194 }
193 else 195 else
194 gk20a_err(g->dev, "unknown engine %d", engine_type); 196 gk20a_err(g->dev, "unknown engine %d", engine_type);
195 197
196 return ret; 198 return ret;
197} 199}
198 200
199void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, 201static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
200 u32 *inst_id, u32 *pri_base, u32 *fault_id) 202 u32 *inst_id, u32 *pri_base, u32 *fault_id)
201{ 203{
202 if (top_device_info_data_type_v(table_entry) == 204 if (top_device_info_data_type_v(table_entry) ==
@@ -226,4 +228,5 @@ void gp10b_init_fifo(struct gpu_ops *gops)
226 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; 228 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
227 gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type; 229 gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
228 gops->fifo.device_info_data_parse = gp10b_device_info_data_parse; 230 gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
231 gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
229} 232}