diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-11-28 02:53:48 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-28 12:47:03 -0500 |
commit | 830d3f10ca1f3d8a045542ef4548c84440a8e548 (patch) | |
tree | f968a340cb80a4d12074ef331b88e21beb1a15d8 /drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |
parent | ce06f74d6ba9eb495661c29eabcd6da2f52c7c8b (diff) |
gpu: nvgpu: cleanup uapi header includes
With recent rework in nvgpu most of the <uapi/linux/nvgpu.h> includes
are not needed so remove them
Remove use of NVGPU_DBG_GPU_REG_OP_* in gk20a/gr_gk20a.c and use common
definition instead
Remove use of NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE in
gp10b/fifo_gp10b.c by defining new common flag
NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE and then parsing it in API
nvgpu_gpfifo_user_flags_to_common_flags()
Jira NVGPU-363
Change-Id: I8e653275ea3f443f24be7284d54f2115636aba3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606108
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 1c9249d1..c82fb1cc 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -22,8 +22,6 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <uapi/linux/nvgpu.h> | ||
26 | |||
27 | #include <nvgpu/dma.h> | 25 | #include <nvgpu/dma.h> |
28 | #include <nvgpu/bug.h> | 26 | #include <nvgpu/bug.h> |
29 | #include <nvgpu/log2.h> | 27 | #include <nvgpu/log2.h> |
@@ -141,10 +139,9 @@ int channel_gp10b_setup_ramfc(struct channel_gk20a *c, | |||
141 | pbdma_runlist_timeslice_timescale_3_f() | | 139 | pbdma_runlist_timeslice_timescale_3_f() | |
142 | pbdma_runlist_timeslice_enable_true_f()); | 140 | pbdma_runlist_timeslice_enable_true_f()); |
143 | 141 | ||
144 | if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) | 142 | if (flags & NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) |
145 | gp10b_set_pdb_fault_replay_flags(c->g, mem); | 143 | gp10b_set_pdb_fault_replay_flags(c->g, mem); |
146 | 144 | ||
147 | |||
148 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); | 145 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); |
149 | 146 | ||
150 | if (c->is_privileged_channel) { | 147 | if (c->is_privileged_channel) { |