diff options
author | Richard Zhao <rizhao@nvidia.com> | 2017-06-27 14:20:58 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 01:34:35 -0400 |
commit | 7d584bf868e53638f5c05b588dcd307e71cf9c82 (patch) | |
tree | ebd3eafd0f71a018f51ac34ec10f55e8669c013d /drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |
parent | d32bd6605d37f576e186d05e0853120cd9782fd3 (diff) |
gpu: nvgpu: rename hw_chid to chid
hw_chid is a relative id for vgpu. For native it's same as hw id.
Renaming it to chid to avoid confusing.
Jira VFND-3796
Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master/r/1509530
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index cfc2eb8d..633fbfb7 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -64,7 +64,7 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c) | |||
64 | addr_hi = u64_hi32(c->userd_iova); | 64 | addr_hi = u64_hi32(c->userd_iova); |
65 | 65 | ||
66 | gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", | 66 | gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", |
67 | c->hw_chid, (u64)c->userd_iova); | 67 | c->chid, (u64)c->userd_iova); |
68 | 68 | ||
69 | nvgpu_mem_wr32(g, &c->inst_block, | 69 | nvgpu_mem_wr32(g, &c->inst_block, |
70 | ram_in_ramfc_w() + ram_fc_userd_w(), | 70 | ram_in_ramfc_w() + ram_fc_userd_w(), |
@@ -134,7 +134,7 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, | |||
134 | gp10b_set_pdb_fault_replay_flags(c->g, mem); | 134 | gp10b_set_pdb_fault_replay_flags(c->g, mem); |
135 | 135 | ||
136 | 136 | ||
137 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); | 137 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); |
138 | 138 | ||
139 | if (c->is_privileged_channel) { | 139 | if (c->is_privileged_channel) { |
140 | /* Set privilege level for channel */ | 140 | /* Set privilege level for channel */ |
@@ -176,7 +176,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) | |||
176 | v = pbdma_allowed_syncpoints_0_valid_f(1); | 176 | v = pbdma_allowed_syncpoints_0_valid_f(1); |
177 | 177 | ||
178 | gk20a_dbg_info("Channel %d, syncpt id %d\n", | 178 | gk20a_dbg_info("Channel %d, syncpt id %d\n", |
179 | c->hw_chid, new_syncpt); | 179 | c->chid, new_syncpt); |
180 | 180 | ||
181 | v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); | 181 | v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); |
182 | 182 | ||