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authorLakshmanan M <lm@nvidia.com>2016-05-23 02:56:46 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:16 -0500
commit642cc7416ebcf0d1e7b813a1cc67d48d58004297 (patch)
tree1634a205d22b5217d3108facf52efc3e1133aed9 /drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
parent85e67e368b4aa41f9a65c77731623d5ffd7029f5 (diff)
gpu: nvgpu: Add device_info_data support
Added device_info_data parsing support for pascal GPU series. This is required to identify the (Logical CE) NV_PTOP_DEVICE_INFO_TYPE_ENUM_LCE instance id. (example - CE0, CE1, CE2, CE3, ...) JIRA DNVGPU-26 Change-Id: I35c42cb1d544729e4099db1528c690dd2be025f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151605 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index 45de221e..89b5527d 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -182,7 +182,8 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
182 return 0; 182 return 0;
183} 183}
184 184
185static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type) 185static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
186 u32 *inst_id)
186{ 187{
187 int ret = ENGINE_INVAL_GK20A; 188 int ret = ENGINE_INVAL_GK20A;
188 189
@@ -197,6 +198,28 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type)
197 return ret; 198 return ret;
198} 199}
199 200
201void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
202 u32 *inst_id, u32 *pri_base, u32 *fault_id)
203{
204 if (top_device_info_data_type_v(table_entry) ==
205 top_device_info_data_type_enum2_v()) {
206 if (inst_id)
207 *inst_id = top_device_info_data_inst_id_v(table_entry);
208 if (pri_base) {
209 *pri_base =
210 (top_device_info_data_pri_base_v(table_entry)
211 << top_device_info_data_pri_base_align_v());
212 }
213 if (fault_id && (top_device_info_data_fault_id_v(table_entry) ==
214 top_device_info_data_fault_id_valid_v())) {
215 *fault_id =
216 top_device_info_data_fault_id_enum_v(table_entry);
217 }
218 } else
219 gk20a_err(g->dev, "unknown device_info_data %d",
220 top_device_info_data_type_v(table_entry));
221}
222
200void gp10b_init_fifo(struct gpu_ops *gops) 223void gp10b_init_fifo(struct gpu_ops *gops)
201{ 224{
202 gm20b_init_fifo(gops); 225 gm20b_init_fifo(gops);
@@ -204,4 +227,5 @@ void gp10b_init_fifo(struct gpu_ops *gops)
204 gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; 227 gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature;
205 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; 228 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
206 gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type; 229 gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
230 gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
207} 231}