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authorSrirangan <smadhavan@nvidia.com>2018-08-23 03:27:45 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-27 10:52:18 -0400
commit5c9bedf6f6e3213cd830d045d70f61de49f6e42b (patch)
treeb5ae6359eb15494766d7c1245304837042c0ca5d /drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
parent14949fbad615ef55adf08c39fd7614d1cbd4109e (diff)
gpu: nvgpu: gp10b: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: Ib5961506b0f95867a57f8c0d7024568785fe7b93 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797332 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c23
1 files changed, 14 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index 011d5f17..c10e389c 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -150,8 +150,9 @@ int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
150 v = nvgpu_mem_rd32(c->g, &c->inst_block, 150 v = nvgpu_mem_rd32(c->g, &c->inst_block,
151 ram_fc_allowed_syncpoints_w()); 151 ram_fc_allowed_syncpoints_w());
152 old_syncpt = pbdma_allowed_syncpoints_0_index_v(v); 152 old_syncpt = pbdma_allowed_syncpoints_0_index_v(v);
153 if (c->sync) 153 if (c->sync) {
154 new_syncpt = c->sync->syncpt_id(c->sync); 154 new_syncpt = c->sync->syncpt_id(c->sync);
155 }
155 156
156 if (new_syncpt && new_syncpt != old_syncpt) { 157 if (new_syncpt && new_syncpt != old_syncpt) {
157 /* disable channel */ 158 /* disable channel */
@@ -185,9 +186,9 @@ int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
185 int ret = ENGINE_INVAL_GK20A; 186 int ret = ENGINE_INVAL_GK20A;
186 187
187 nvgpu_log_info(g, "engine type %d", engine_type); 188 nvgpu_log_info(g, "engine type %d", engine_type);
188 if (engine_type == top_device_info_type_enum_graphics_v()) 189 if (engine_type == top_device_info_type_enum_graphics_v()) {
189 ret = ENGINE_GR_GK20A; 190 ret = ENGINE_GR_GK20A;
190 else if (engine_type == top_device_info_type_enum_lce_v()) { 191 } else if (engine_type == top_device_info_type_enum_lce_v()) {
191 /* Default assumptions - all the CE engine have separate runlist */ 192 /* Default assumptions - all the CE engine have separate runlist */
192 ret = ENGINE_ASYNC_CE_GK20A; 193 ret = ENGINE_ASYNC_CE_GK20A;
193 } 194 }
@@ -200,8 +201,9 @@ void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
200{ 201{
201 if (top_device_info_data_type_v(table_entry) == 202 if (top_device_info_data_type_v(table_entry) ==
202 top_device_info_data_type_enum2_v()) { 203 top_device_info_data_type_enum2_v()) {
203 if (inst_id) 204 if (inst_id) {
204 *inst_id = top_device_info_data_inst_id_v(table_entry); 205 *inst_id = top_device_info_data_inst_id_v(table_entry);
206 }
205 if (pri_base) { 207 if (pri_base) {
206 *pri_base = 208 *pri_base =
207 (top_device_info_data_pri_base_v(table_entry) 209 (top_device_info_data_pri_base_v(table_entry)
@@ -214,9 +216,10 @@ void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
214 g->ops.fifo.device_info_fault_id(table_entry); 216 g->ops.fifo.device_info_fault_id(table_entry);
215 nvgpu_log_info(g, "device info: fault_id: %d", *fault_id); 217 nvgpu_log_info(g, "device info: fault_id: %d", *fault_id);
216 } 218 }
217 } else 219 } else {
218 nvgpu_err(g, "unknown device_info_data %d", 220 nvgpu_err(g, "unknown device_info_data %d",
219 top_device_info_data_type_v(table_entry)); 221 top_device_info_data_type_v(table_entry));
222 }
220} 223}
221 224
222void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) 225void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
@@ -330,21 +333,23 @@ static const char * const gp10b_hub_client_descs[] = {
330/* fill in mmu fault desc */ 333/* fill in mmu fault desc */
331void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault) 334void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault)
332{ 335{
333 if (mmfault->fault_type >= ARRAY_SIZE(gp10b_fault_type_descs)) 336 if (mmfault->fault_type >= ARRAY_SIZE(gp10b_fault_type_descs)) {
334 WARN_ON(mmfault->fault_type >= 337 WARN_ON(mmfault->fault_type >=
335 ARRAY_SIZE(gp10b_fault_type_descs)); 338 ARRAY_SIZE(gp10b_fault_type_descs));
336 else 339 } else {
337 mmfault->fault_type_desc = 340 mmfault->fault_type_desc =
338 gp10b_fault_type_descs[mmfault->fault_type]; 341 gp10b_fault_type_descs[mmfault->fault_type];
342 }
339} 343}
340 344
341/* fill in mmu fault client description */ 345/* fill in mmu fault client description */
342void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault) 346void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault)
343{ 347{
344 if (mmfault->client_id >= ARRAY_SIZE(gp10b_hub_client_descs)) 348 if (mmfault->client_id >= ARRAY_SIZE(gp10b_hub_client_descs)) {
345 WARN_ON(mmfault->client_id >= 349 WARN_ON(mmfault->client_id >=
346 ARRAY_SIZE(gp10b_hub_client_descs)); 350 ARRAY_SIZE(gp10b_hub_client_descs));
347 else 351 } else {
348 mmfault->client_id_desc = 352 mmfault->client_id_desc =
349 gp10b_hub_client_descs[mmfault->client_id]; 353 gp10b_hub_client_descs[mmfault->client_id];
354 }
350} 355}