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authorAlex Waterman <alexw@nvidia.com>2018-02-28 12:19:19 -0500
committerSrikar Srimath Tirumala <srikars@nvidia.com>2018-02-28 16:49:22 -0500
commit5a35a95654d561fce09a3b9abf6b82bb7a29d74b (patch)
tree119a07134188d8e06c29a570dd8c6b143f39c9e1 /drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
parent3fdd8e38b280123fd13bcc4f3fd8928c15e94db6 (diff)
Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working"
Also revert other changes related to IO coherence. This may be the culprit in a recent dev-kernel lockdown. Bug 2070609 Change-Id: Ida178aef161fadbc6db9512521ea51c702c1564b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665914 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index 1436a260..c82fb1cc 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -25,7 +25,6 @@
25#include <nvgpu/dma.h> 25#include <nvgpu/dma.h>
26#include <nvgpu/bug.h> 26#include <nvgpu/bug.h>
27#include <nvgpu/log2.h> 27#include <nvgpu/log2.h>
28#include <nvgpu/enabled.h>
29 28
30#include "fifo_gp10b.h" 29#include "fifo_gp10b.h"
31 30
@@ -79,9 +78,8 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c)
79 nvgpu_mem_wr32(g, &c->inst_block, 78 nvgpu_mem_wr32(g, &c->inst_block,
80 ram_in_ramfc_w() + ram_fc_userd_w(), 79 ram_in_ramfc_w() + ram_fc_userd_w(),
81 nvgpu_aperture_mask(g, &g->fifo.userd, 80 nvgpu_aperture_mask(g, &g->fifo.userd,
82 pbdma_userd_target_sys_mem_ncoh_f(), 81 pbdma_userd_target_sys_mem_ncoh_f(),
83 pbdma_userd_target_sys_mem_coh_f(), 82 pbdma_userd_target_vid_mem_f()) |
84 pbdma_userd_target_vid_mem_f()) |
85 pbdma_userd_addr_f(addr_lo)); 83 pbdma_userd_addr_f(addr_lo));
86 84
87 nvgpu_mem_wr32(g, &c->inst_block, 85 nvgpu_mem_wr32(g, &c->inst_block,