diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-11-03 11:46:21 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:53 -0500 |
commit | e5824d8014c321fbe2c1e04e12307125dd50a472 (patch) | |
tree | 82657cd43c0dcd313b3251f3776e5e80b488fabc /drivers/gpu/nvgpu/gp106 | |
parent | 62d13e613807e9bce3a9d1ef0c61725ef3a885ce (diff) |
gpu: nvgpu: MSCG support
- update gp106 pg engine init/list/features HALs
to support MS engine
- Added defines & interface for lpwr tables read from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
features enable/disable mscg/rppg & mclk-change
request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
requested pstate,
- added mutex t prevent PG transition while arbiter
executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
get current pstate
JIRA DNVGPU-71
Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 6f5e71eb..eecd7351 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "clk/clk_mclk.h" | 24 | #include "clk/clk_mclk.h" |
25 | #include "hw_mc_gp106.h" | 25 | #include "hw_mc_gp106.h" |
26 | #include "hw_pwr_gp106.h" | 26 | #include "hw_pwr_gp106.h" |
27 | #include "lpwr/lpwr.h" | ||
27 | #include "lpwr/rppg.h" | 28 | #include "lpwr/rppg.h" |
28 | 29 | ||
29 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 | 30 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 |
@@ -180,12 +181,16 @@ static u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) | |||
180 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 181 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
181 | return PMU_PG_FEATURE_GR_RPPG_ENABLED; | 182 | return PMU_PG_FEATURE_GR_RPPG_ENABLED; |
182 | 183 | ||
184 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | ||
185 | return NVGPU_PMU_MS_FEATURE_MASK_ALL; | ||
186 | |||
183 | return 0; | 187 | return 0; |
184 | } | 188 | } |
185 | 189 | ||
186 | static u32 gp106_pmu_pg_engines_list(struct gk20a *g) | 190 | static u32 gp106_pmu_pg_engines_list(struct gk20a *g) |
187 | { | 191 | { |
188 | return BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS); | 192 | return BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | |
193 | BIT(PMU_PG_ELPG_ENGINE_ID_MS); | ||
189 | } | 194 | } |
190 | 195 | ||
191 | static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg, | 196 | static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg, |
@@ -231,6 +236,23 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) | |||
231 | gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM"); | 236 | gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM"); |
232 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 237 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
233 | pmu_handle_param_msg, pmu, &seq, ~0); | 238 | pmu_handle_param_msg, pmu, &seq, ~0); |
239 | } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { | ||
240 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
241 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
242 | sizeof(struct pmu_pg_cmd_ms_init_param); | ||
243 | cmd.cmd.pg.ms_init_param.cmd_type = | ||
244 | PMU_PG_CMD_ID_PG_PARAM; | ||
245 | cmd.cmd.pg.ms_init_param.cmd_id = | ||
246 | PMU_PG_PARAM_CMD_MS_INIT_PARAM; | ||
247 | cmd.cmd.pg.ms_init_param.support_mask = | ||
248 | NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING | | ||
249 | NVGPU_PMU_MS_FEATURE_MASK_SW_ASR | | ||
250 | NVGPU_PMU_MS_FEATURE_MASK_RPPG | | ||
251 | NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING; | ||
252 | |||
253 | gp106_dbg_pmu("cmd post MS PMU_PG_CMD_ID_PG_PARAM"); | ||
254 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
255 | pmu_handle_param_msg, pmu, &seq, ~0); | ||
234 | } | 256 | } |
235 | 257 | ||
236 | return 0; | 258 | return 0; |
@@ -261,6 +283,9 @@ void gp106_init_pmu_ops(struct gpu_ops *gops) | |||
261 | gops->pmu.pmu_pg_init_param = gp106_pg_param_init; | 283 | gops->pmu.pmu_pg_init_param = gp106_pg_param_init; |
262 | gops->pmu.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list; | 284 | gops->pmu.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list; |
263 | gops->pmu.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list; | 285 | gops->pmu.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list; |
286 | gops->pmu.pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg; | ||
287 | gops->pmu.pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg; | ||
288 | gops->pmu.pmu_pg_param_post_init = nvgpu_lpwr_post_init; | ||
264 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | 289 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
265 | gops->pmu.dump_secure_fuses = NULL; | 290 | gops->pmu.dump_secure_fuses = NULL; |
266 | gops->pmu.reset = gp106_falcon_reset; | 291 | gops->pmu.reset = gp106_falcon_reset; |