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authorVaibhav Kachore <vkachore@nvidia.com>2018-02-22 06:15:30 -0500
committerTejal Kudav <tkudav@nvidia.com>2018-06-14 09:44:08 -0400
commitca3215c6b23c7d855ced899d8090aaa8ce9a9fa3 (patch)
tree710114451d4838f82a9e9998db52b81cf76d68c9 /drivers/gpu/nvgpu/gp106
parent97d697a8481ca0c348102f04165903e3205302ed (diff)
gpu: nvgpu: add support for FECS VA
- On t186, ucode expects physical address to be programmed for FECS trace buffer. - On t194, ucode expects GPU VA to be programmed for FECS trace buffer. This patch adds extra support to handle this change for linux native. - Increase the size of FECS trace buffer (as few entries were getting dropped due to overflow of FECS trace buffer.) - This moves FECS trace buffer handling in global context buffer. - This adds extra check for updation of mailbox1 register. (Bug 200417403) EVLR-2077 Change-Id: I7c3324ce9341976a1375e0afe6c53c424a053723 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 61c6cb0f..632f1063 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -834,6 +834,7 @@ int gp106_init_hal(struct gk20a *g)
834 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); 834 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
835 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); 835 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
836 __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); 836 __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
837 __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
837 838
838 /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ 839 /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
839 if (gops->fuse.check_priv_security(g)) 840 if (gops->fuse.check_priv_security(g))