diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-09-06 06:43:31 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:19 -0500 |
commit | bb6923908a2873b079ad67d22c9fcb014c00af28 (patch) | |
tree | 94a990e130547150ea61d5d476fb14633784984c /drivers/gpu/nvgpu/gp106 | |
parent | 5544272474d7b1e3103eed76fbaf91ba7a739345 (diff) |
gpu: nvgpu: select target based on aperture
For bar2 and pmu instance blocks, use gk20a_aperture_mask()
to select target address (i.e. if address is in sysmem or
vidmem) based on aperture
Also add target accessors for gr_fecs_new_ctx and
gr_fecs_arb_ctx_ptr
Jira DNVGPU-22
Change-Id: Ieaa80bd83a4191fe57b7fba6e0f9cdaeb195a077
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1216138
(cherry picked from commit 7a9f4175abc5dddf0879215de4637b7b6eb0ab7b)
Reviewed-on: http://git-master/r/1219712
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hw_gr_gp106.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 8 |
2 files changed, 22 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h index e5e1c527..bb1f9fa9 100644 --- a/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h | |||
@@ -1342,6 +1342,14 @@ static inline u32 gr_fecs_new_ctx_target_v(u32 r) | |||
1342 | { | 1342 | { |
1343 | return (r >> 28) & 0x3; | 1343 | return (r >> 28) & 0x3; |
1344 | } | 1344 | } |
1345 | static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) | ||
1346 | { | ||
1347 | return 0x0; | ||
1348 | } | ||
1349 | static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) | ||
1350 | { | ||
1351 | return 0x30000000; | ||
1352 | } | ||
1345 | static inline u32 gr_fecs_new_ctx_valid_s(void) | 1353 | static inline u32 gr_fecs_new_ctx_valid_s(void) |
1346 | { | 1354 | { |
1347 | return 1; | 1355 | return 1; |
@@ -1394,6 +1402,14 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) | |||
1394 | { | 1402 | { |
1395 | return (r >> 28) & 0x3; | 1403 | return (r >> 28) & 0x3; |
1396 | } | 1404 | } |
1405 | static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) | ||
1406 | { | ||
1407 | return 0x0; | ||
1408 | } | ||
1409 | static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) | ||
1410 | { | ||
1411 | return 0x30000000; | ||
1412 | } | ||
1397 | static inline u32 gr_fecs_arb_ctx_cmd_r(void) | 1413 | static inline u32 gr_fecs_arb_ctx_cmd_r(void) |
1398 | { | 1414 | { |
1399 | return 0x00409a10; | 1415 | return 0x00409a10; |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index f8b32f8f..8f34edd1 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -169,7 +169,9 @@ int bl_bootstrap_sec2(struct pmu_gk20a *pmu, | |||
169 | pwr_pmu_new_instblk_ptr_f( | 169 | pwr_pmu_new_instblk_ptr_f( |
170 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 170 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
171 | pwr_pmu_new_instblk_valid_f(1) | | 171 | pwr_pmu_new_instblk_valid_f(1) | |
172 | pwr_pmu_new_instblk_target_sys_coh_f()); | 172 | gk20a_aperture_mask(g, &mm->pmu.inst_block, |
173 | pwr_pmu_new_instblk_target_sys_coh_f(), | ||
174 | pwr_pmu_new_instblk_target_fb_f())); | ||
173 | 175 | ||
174 | data = gk20a_readl(g, psec_falcon_debug1_r()); | 176 | data = gk20a_readl(g, psec_falcon_debug1_r()); |
175 | data |= psec_falcon_debug1_ctxsw_mode_m(); | 177 | data |= psec_falcon_debug1_ctxsw_mode_m(); |
@@ -313,7 +315,9 @@ void init_pmu_setup_hw1(struct gk20a *g) | |||
313 | pwr_pmu_new_instblk_ptr_f( | 315 | pwr_pmu_new_instblk_ptr_f( |
314 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 316 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
315 | pwr_pmu_new_instblk_valid_f(1) | | 317 | pwr_pmu_new_instblk_valid_f(1) | |
316 | pwr_pmu_new_instblk_target_sys_coh_f()); | 318 | gk20a_aperture_mask(g, &mm->pmu.inst_block, |
319 | pwr_pmu_new_instblk_target_sys_coh_f(), | ||
320 | pwr_pmu_new_instblk_target_fb_f())); | ||
317 | 321 | ||
318 | /*Copying pmu cmdline args*/ | 322 | /*Copying pmu cmdline args*/ |
319 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, | 323 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, |