diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-14 15:06:39 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-19 15:16:02 -0400 |
commit | a9c66768db400a82575a82ecddec71f1d3fd4aba (patch) | |
tree | 3b83db70149515fc21c9d700f68bbcf0fb4e58b4 /drivers/gpu/nvgpu/gp106 | |
parent | 7eb59ff8d334e9980e21bac50b4680855bd8237f (diff) |
gpu: nvgpu: Add abstraction for firmware loading
Add nvgpu_firmware data structure, and return it instead of Linux
struct firmare from nvgpu_request_firmware. Also add abstraction
for releasing firmware: nvgpu_release_firmware.
JIRA NVGPU-16
Change-Id: I6dae8262957c0d4506f710289e3a43a6c1729fc7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463538
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index da281077..c4045cb6 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -11,13 +11,13 @@ | |||
11 | * more details. | 11 | * more details. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <linux/firmware.h> | ||
15 | #include <linux/debugfs.h> | 14 | #include <linux/debugfs.h> |
16 | 15 | ||
17 | #include <nvgpu/nvgpu_common.h> | 16 | #include <nvgpu/nvgpu_common.h> |
18 | #include <nvgpu/kmem.h> | 17 | #include <nvgpu/kmem.h> |
19 | #include <nvgpu/dma.h> | 18 | #include <nvgpu/dma.h> |
20 | #include <nvgpu/acr/nvgpu_acr.h> | 19 | #include <nvgpu/acr/nvgpu_acr.h> |
20 | #include <nvgpu/firmware.h> | ||
21 | 21 | ||
22 | #include "gk20a/gk20a.h" | 22 | #include "gk20a/gk20a.h" |
23 | #include "gk20a/pmu_gk20a.h" | 23 | #include "gk20a/pmu_gk20a.h" |
@@ -137,7 +137,7 @@ void gp106_init_secure_pmu(struct gpu_ops *gops) | |||
137 | 137 | ||
138 | static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | 138 | static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) |
139 | { | 139 | { |
140 | const struct firmware *pmu_fw, *pmu_desc, *pmu_sig; | 140 | struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig; |
141 | struct pmu_gk20a *pmu = &g->pmu; | 141 | struct pmu_gk20a *pmu = &g->pmu; |
142 | struct lsf_ucode_desc_v1 *lsf_desc; | 142 | struct lsf_ucode_desc_v1 *lsf_desc; |
143 | int err; | 143 | int err; |
@@ -194,14 +194,14 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
194 | p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; | 194 | p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; |
195 | gp106_dbg_pmu("requesting PMU ucode in GM20B exit\n"); | 195 | gp106_dbg_pmu("requesting PMU ucode in GM20B exit\n"); |
196 | 196 | ||
197 | release_firmware(pmu_sig); | 197 | nvgpu_release_firmware(g, pmu_sig); |
198 | return 0; | 198 | return 0; |
199 | release_sig: | 199 | release_sig: |
200 | release_firmware(pmu_sig); | 200 | nvgpu_release_firmware(g, pmu_sig); |
201 | release_desc: | 201 | release_desc: |
202 | release_firmware(pmu_desc); | 202 | nvgpu_release_firmware(g, pmu_desc); |
203 | release_img_fw: | 203 | release_img_fw: |
204 | release_firmware(pmu_fw); | 204 | nvgpu_release_firmware(g, pmu_fw); |
205 | return err; | 205 | return err; |
206 | } | 206 | } |
207 | 207 | ||
@@ -209,7 +209,7 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
209 | { | 209 | { |
210 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | 210 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; |
211 | struct lsf_ucode_desc_v1 *lsf_desc; | 211 | struct lsf_ucode_desc_v1 *lsf_desc; |
212 | const struct firmware *fecs_sig = NULL; | 212 | struct nvgpu_firmware *fecs_sig = NULL; |
213 | int err; | 213 | int err; |
214 | 214 | ||
215 | switch (ver) { | 215 | switch (ver) { |
@@ -279,12 +279,12 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
279 | p_img->header = NULL; | 279 | p_img->header = NULL; |
280 | p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; | 280 | p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; |
281 | gp106_dbg_pmu("fecs fw loaded\n"); | 281 | gp106_dbg_pmu("fecs fw loaded\n"); |
282 | release_firmware(fecs_sig); | 282 | nvgpu_release_firmware(g, fecs_sig); |
283 | return 0; | 283 | return 0; |
284 | free_lsf_desc: | 284 | free_lsf_desc: |
285 | nvgpu_kfree(g, lsf_desc); | 285 | nvgpu_kfree(g, lsf_desc); |
286 | rel_sig: | 286 | rel_sig: |
287 | release_firmware(fecs_sig); | 287 | nvgpu_release_firmware(g, fecs_sig); |
288 | return err; | 288 | return err; |
289 | } | 289 | } |
290 | 290 | ||
@@ -292,7 +292,7 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
292 | { | 292 | { |
293 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | 293 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; |
294 | struct lsf_ucode_desc_v1 *lsf_desc; | 294 | struct lsf_ucode_desc_v1 *lsf_desc; |
295 | const struct firmware *gpccs_sig = NULL; | 295 | struct nvgpu_firmware *gpccs_sig = NULL; |
296 | int err; | 296 | int err; |
297 | 297 | ||
298 | if (g->ops.securegpccs == false) | 298 | if (g->ops.securegpccs == false) |
@@ -366,12 +366,12 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
366 | p_img->header = NULL; | 366 | p_img->header = NULL; |
367 | p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; | 367 | p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; |
368 | gp106_dbg_pmu("gpccs fw loaded\n"); | 368 | gp106_dbg_pmu("gpccs fw loaded\n"); |
369 | release_firmware(gpccs_sig); | 369 | nvgpu_release_firmware(g, gpccs_sig); |
370 | return 0; | 370 | return 0; |
371 | free_lsf_desc: | 371 | free_lsf_desc: |
372 | nvgpu_kfree(g, lsf_desc); | 372 | nvgpu_kfree(g, lsf_desc); |
373 | rel_sig: | 373 | rel_sig: |
374 | release_firmware(gpccs_sig); | 374 | nvgpu_release_firmware(g, gpccs_sig); |
375 | return err; | 375 | return err; |
376 | } | 376 | } |
377 | 377 | ||
@@ -1048,7 +1048,7 @@ static int gp106_bootstrap_hs_flcn(struct gk20a *g) | |||
1048 | u32 img_size_in_bytes = 0; | 1048 | u32 img_size_in_bytes = 0; |
1049 | u32 status; | 1049 | u32 status; |
1050 | struct acr_desc *acr = &g->acr; | 1050 | struct acr_desc *acr = &g->acr; |
1051 | const struct firmware *acr_fw = acr->acr_fw; | 1051 | struct nvgpu_firmware *acr_fw = acr->acr_fw; |
1052 | struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1; | 1052 | struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1; |
1053 | u32 *acr_ucode_header_t210_load; | 1053 | u32 *acr_ucode_header_t210_load; |
1054 | u32 *acr_ucode_data_t210_load; | 1054 | u32 *acr_ucode_data_t210_load; |
@@ -1167,7 +1167,7 @@ static int gp106_bootstrap_hs_flcn(struct gk20a *g) | |||
1167 | err_free_ucode_map: | 1167 | err_free_ucode_map: |
1168 | nvgpu_dma_unmap_free(vm, &acr->acr_ucode); | 1168 | nvgpu_dma_unmap_free(vm, &acr->acr_ucode); |
1169 | err_release_acr_fw: | 1169 | err_release_acr_fw: |
1170 | release_firmware(acr_fw); | 1170 | nvgpu_release_firmware(g, acr_fw); |
1171 | acr->acr_fw = NULL; | 1171 | acr->acr_fw = NULL; |
1172 | return err; | 1172 | return err; |
1173 | } | 1173 | } |