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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-09 12:20:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-14 18:33:20 -0400
commit91390d857f6302f9c2923ec4188ea7e24ee537a2 (patch)
treee0884e79ea748d2c0bd384c29f805125a7b88fec /drivers/gpu/nvgpu/gp106
parent02f9c99e4b4a452ded20978c5ee1e27b775b9224 (diff)
gpu: nvgpu: Move therm HAL to common
Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c6
-rw-r--r--drivers/gpu/nvgpu/gp106/therm_gp106.c144
-rw-r--r--drivers/gpu/nvgpu/gp106/therm_gp106.h38
3 files changed, 4 insertions, 184 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 90d25fa0..02a2f0a6 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -34,6 +34,8 @@
34#include "common/fb/fb_gm20b.h" 34#include "common/fb/fb_gm20b.h"
35#include "common/fb/fb_gp106.h" 35#include "common/fb/fb_gp106.h"
36#include "common/xve/xve_gp106.h" 36#include "common/xve/xve_gp106.h"
37#include "common/therm/therm_gm20b.h"
38#include "common/therm/therm_gp106.h"
37 39
38#include "gk20a/gk20a.h" 40#include "gk20a/gk20a.h"
39#include "gk20a/fifo_gk20a.h" 41#include "gk20a/fifo_gk20a.h"
@@ -76,7 +78,6 @@
76#include "gp106/clk_arb_gp106.h" 78#include "gp106/clk_arb_gp106.h"
77#include "gp106/mclk_gp106.h" 79#include "gp106/mclk_gp106.h"
78#include "gp106/bios_gp106.h" 80#include "gp106/bios_gp106.h"
79#include "gp106/therm_gp106.h"
80#include "gp106/fifo_gp106.h" 81#include "gp106/fifo_gp106.h"
81#include "gp106/clk_gp106.h" 82#include "gp106/clk_gp106.h"
82#include "gp106/mm_gp106.h" 83#include "gp106/mm_gp106.h"
@@ -349,7 +350,6 @@ static const struct gpu_ops gp106_ops = {
349 .commit_inst = gr_gk20a_commit_inst, 350 .commit_inst = gr_gk20a_commit_inst,
350 .write_zcull_ptr = gr_gk20a_write_zcull_ptr, 351 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
351 .write_pm_ptr = gr_gk20a_write_pm_ptr, 352 .write_pm_ptr = gr_gk20a_write_pm_ptr,
352 .init_elcg_mode = gr_gk20a_init_elcg_mode,
353 .load_tpc_mask = gr_gm20b_load_tpc_mask, 353 .load_tpc_mask = gr_gm20b_load_tpc_mask,
354 .inval_icache = gr_gk20a_inval_icache, 354 .inval_icache = gr_gk20a_inval_icache,
355 .trigger_suspend = gr_gk20a_trigger_suspend, 355 .trigger_suspend = gr_gk20a_trigger_suspend,
@@ -606,6 +606,8 @@ static const struct gpu_ops gp106_ops = {
606#ifdef CONFIG_DEBUG_FS 606#ifdef CONFIG_DEBUG_FS
607 .therm_debugfs_init = gp106_therm_debugfs_init, 607 .therm_debugfs_init = gp106_therm_debugfs_init,
608#endif /* CONFIG_DEBUG_FS */ 608#endif /* CONFIG_DEBUG_FS */
609 .init_elcg_mode = gm20b_therm_init_elcg_mode,
610 .init_blcg_mode = gm20b_therm_init_blcg_mode,
609 .elcg_init_idle_filters = gp106_elcg_init_idle_filters, 611 .elcg_init_idle_filters = gp106_elcg_init_idle_filters,
610 .get_internal_sensor_curr_temp = 612 .get_internal_sensor_curr_temp =
611 gp106_get_internal_sensor_curr_temp, 613 gp106_get_internal_sensor_curr_temp,
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.c b/drivers/gpu/nvgpu/gp106/therm_gp106.c
deleted file mode 100644
index 1f82aa7a..00000000
--- a/drivers/gpu/nvgpu/gp106/therm_gp106.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/io.h>
24#include "gk20a/gk20a.h"
25
26#include "therm_gp106.h"
27#include "therm/thrmpmu.h"
28
29#ifdef CONFIG_DEBUG_FS
30#include <linux/debugfs.h>
31#include "os/linux/os_linux.h"
32#endif
33
34#include <nvgpu/hw/gp106/hw_therm_gp106.h>
35
36#include <nvgpu/utils.h>
37
38void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8)
39{
40 *max_24_8 = (0x87 << 8);
41 *min_24_8 = (((u32)-216) << 8);
42}
43
44int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
45{
46 int err = 0;
47 u32 readval;
48
49 readval = gk20a_readl(g, therm_temp_sensor_tsense_r());
50
51 if (!(therm_temp_sensor_tsense_state_v(readval) &
52 therm_temp_sensor_tsense_state_valid_v())) {
53 nvgpu_err(g,
54 "Attempt to read temperature while sensor is OFF!");
55 err = -EINVAL;
56 } else if (therm_temp_sensor_tsense_state_v(readval) &
57 therm_temp_sensor_tsense_state_shadow_v()) {
58 nvgpu_err(g, "Reading temperature from SHADOWed sensor!");
59 }
60
61 // Convert from F9.5 -> F27.5 -> F24.8.
62 readval &= therm_temp_sensor_tsense_fixed_point_m();
63
64 *temp_f24_8 = readval;
65
66 return err;
67}
68
69#ifdef CONFIG_DEBUG_FS
70static int therm_get_internal_sensor_curr_temp(void *data, u64 *val)
71{
72 struct gk20a *g = (struct gk20a *)data;
73 u32 readval;
74 int err;
75
76 err = gp106_get_internal_sensor_curr_temp(g, &readval);
77 if (!err)
78 *val = readval;
79
80 return err;
81}
82DEFINE_SIMPLE_ATTRIBUTE(therm_ctrl_fops, therm_get_internal_sensor_curr_temp, NULL, "%llu\n");
83
84void gp106_therm_debugfs_init(struct gk20a *g)
85{
86 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
87 struct dentry *dbgentry;
88
89 dbgentry = debugfs_create_file(
90 "temp", S_IRUGO, l->debugfs, g, &therm_ctrl_fops);
91 if (!dbgentry)
92 nvgpu_err(g, "debugfs entry create failed for therm_curr_temp");
93}
94#endif
95
96int gp106_elcg_init_idle_filters(struct gk20a *g)
97{
98 u32 gate_ctrl, idle_filter;
99 u32 engine_id;
100 u32 active_engine_id = 0;
101 struct fifo_gk20a *f = &g->fifo;
102
103 nvgpu_log_fn(g, " ");
104
105 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
106 active_engine_id = f->active_engines_list[engine_id];
107 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
108
109 gate_ctrl = set_field(gate_ctrl,
110 therm_gate_ctrl_eng_idle_filt_exp_m(),
111 therm_gate_ctrl_eng_idle_filt_exp_f(2));
112 gate_ctrl = set_field(gate_ctrl,
113 therm_gate_ctrl_eng_idle_filt_mant_m(),
114 therm_gate_ctrl_eng_idle_filt_mant_f(1));
115 gate_ctrl = set_field(gate_ctrl,
116 therm_gate_ctrl_eng_delay_before_m(),
117 therm_gate_ctrl_eng_delay_before_f(0));
118 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
119 }
120
121 /* default fecs_idle_filter to 0 */
122 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
123 idle_filter &= ~therm_fecs_idle_filter_value_m();
124 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
125 /* default hubmmu_idle_filter to 0 */
126 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
127 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
128 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
129
130 nvgpu_log_fn(g, "done");
131 return 0;
132}
133
134u32 gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp)
135{
136 u32 err = 0;
137
138 if (g->curr_warn_temp != curr_warn_temp) {
139 g->curr_warn_temp = curr_warn_temp;
140 err = therm_configure_therm_alert(g);
141 }
142
143 return err;
144}
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.h b/drivers/gpu/nvgpu/gp106/therm_gp106.h
deleted file mode 100644
index 5debcee7..00000000
--- a/drivers/gpu/nvgpu/gp106/therm_gp106.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * general thermal control structures & definitions
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef NVGPU_THERM_GP106_H
26#define NVGPU_THERM_GP106_H
27
28struct gk20a;
29
30void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8);
31int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8);
32#ifdef CONFIG_DEBUG_FS
33void gp106_therm_debugfs_init(struct gk20a *g);
34#endif
35int gp106_elcg_init_idle_filters(struct gk20a *g);
36u32 gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp);
37
38#endif