gpu: nvgpu: use common nvgpu mutex/spinlock APIs

Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>

Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()

And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>

Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h

Jira NVGPU-13

Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 12 insertions, 12 deletions

diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index edeb97ec..3b9c444d 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -1,7 +1,7 @@
 /*
  * GP106 Clocks
  *
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -79,7 +79,7 @@ static int gp106_init_clk_support(struct gk20a *g) {
 
         gk20a_dbg_fn("");
 
-        mutex_init(&clk->clk_mutex);
+        nvgpu_mutex_init(&clk->clk_mutex);
 
         clk->clk_namemap = (struct namemap_cfg *)
                 kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL);
@@ -169,7 +169,7 @@ static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
         if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr)
                 return 0;
 
-        mutex_lock(&clk->clk_mutex);
+        nvgpu_mutex_acquire(&clk->clk_mutex);
 
         /* Save the register */
         save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr);
@@ -216,7 +216,7 @@ read_err:
         gk20a_readl(g, c->cntr.reg_ctrl_addr);
         gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg);
         gk20a_readl(g, c->cntr.reg_ctrl_addr);
-        mutex_unlock(&clk->clk_mutex);
+        nvgpu_mutex_release(&clk->clk_mutex);
 
         return cntr;
 
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h
index 7df4b974..3c2e31d1 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,7 +16,7 @@
 #ifndef CLK_GP106_H
 #define CLK_GP106_H
 
-#include <linux/mutex.h>
+#include <nvgpu/lock.h>
 
 #define CLK_NAMEMAP_INDEX_GPC2CLK       0x00
 #define CLK_NAMEMAP_INDEX_XBAR2CLK      0x02
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 9af16886..51e76605 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -114,7 +114,7 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
                 return;
         }
 
-        mutex_lock(&pmu->pmu_copy_lock);
+        nvgpu_mutex_acquire(&pmu->pmu_copy_lock);
 
         words = size >> 2;
         bytes = size & 0x3;
@@ -144,7 +144,7 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
                         "copy failed. bytes written %d, expected %d",
                         data - dst, size);
         }
-        mutex_unlock(&pmu->pmu_copy_lock);
+        nvgpu_mutex_release(&pmu->pmu_copy_lock);
         return;
 }
 
@@ -348,10 +348,10 @@ int init_sec2_setup_hw1(struct gk20a *g,
 
         gk20a_dbg_fn("");
 
-        mutex_lock(&pmu->isr_mutex);
+        nvgpu_mutex_acquire(&pmu->isr_mutex);
         g->ops.pmu.reset(g);
         pmu->isr_enabled = true;
-        mutex_unlock(&pmu->isr_mutex);
+        nvgpu_mutex_release(&pmu->isr_mutex);
 
         data = gk20a_readl(g, psec_fbif_ctl_r());
         data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f();
@@ -379,11 +379,11 @@ int init_sec2_setup_hw1(struct gk20a *g,
                         psec_fbif_transcfg_target_noncoherent_sysmem_f());
 
         /*disable irqs for hs falcon booting as we will poll for halt*/
-        mutex_lock(&pmu->isr_mutex);
+        nvgpu_mutex_acquire(&pmu->isr_mutex);
         pmu_enable_irq(pmu, false);
         sec_enable_irq(pmu, false);
         pmu->isr_enabled = false;
-        mutex_unlock(&pmu->isr_mutex);
+        nvgpu_mutex_release(&pmu->isr_mutex);
         err = bl_bootstrap_sec2(pmu, desc, bl_sz);
         if (err)
                 return err;