Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel

Merge T186 - gp10b/gp106 code into common nvgpu repo

Bug 200266498

Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>

62 files changed, 19514 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
new file mode 100644
index 00000000..5ed6300c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -0,0 +1,1169 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>        /* for mdelay */
+#include <linux/firmware.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+#include "gk20a/semaphore_gk20a.h"
+#include "gp106/hw_psec_gp106.h"
+#include "gp106/hw_pwr_gp106.h"
+#include "gm206/acr_gm206.h"
+#include "gm20b/acr_gm20b.h"
+#include "gm206/pmu_gm206.h"
+#include "sec2_gp106.h"
+#include "nvgpu_gpuid_t18x.h"
+#include "nvgpu_common.h"
+
+/*Defines*/
+#define gp106_dbg_pmu(fmt, arg...) \
+        gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
+
+typedef int (*get_ucode_details)(struct gk20a *g,
+                struct flcn_ucode_img_v1 *udata);
+
+/* Both size and address of WPR need to be 128K-aligned */
+#define WPR_ALIGNMENT   0x20000
+#define GP106_DGPU_NONWPR NVGPU_VIDMEM_BOOTSTRAP_ALLOCATOR_BASE
+#define GP106_DGPU_WPR_OFFSET 0x400000
+#define DGPU_WPR_SIZE 0x100000
+
+/*Externs*/
+
+/*Forwards*/
+static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
+static int fecs_ucode_details(struct gk20a *g,
+                struct flcn_ucode_img_v1 *p_img);
+static int gpccs_ucode_details(struct gk20a *g,
+                struct flcn_ucode_img_v1 *p_img);
+static int gp106_bootstrap_hs_flcn(struct gk20a *g);
+
+static int lsfm_discover_ucode_images(struct gk20a *g,
+        struct ls_flcn_mgr_v1 *plsfm);
+static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
+        struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id);
+static void lsfm_free_ucode_img_res(struct flcn_ucode_img_v1 *p_img);
+static void lsfm_free_nonpmu_ucode_img_res(struct flcn_ucode_img_v1 *p_img);
+static int lsf_gen_wpr_requirements(struct gk20a *g,
+                struct ls_flcn_mgr_v1 *plsfm);
+static void lsfm_init_wpr_contents(struct gk20a *g,
+                struct ls_flcn_mgr_v1 *plsfm, struct mem_desc *nonwpr);
+static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm);
+static int gp106_pmu_populate_loader_cfg(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size);
+static int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
+static int gp106_prepare_ucode_blob(struct gk20a *g);
+
+/*Globals*/
+static get_ucode_details pmu_acr_supp_ucode_list[] = {
+        pmu_ucode_details,
+        fecs_ucode_details,
+        gpccs_ucode_details,
+};
+
+static void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
+{
+        inf->nonwpr_base = g->mm.vidmem.bootstrap_base;
+        inf->wpr_base = inf->nonwpr_base + GP106_DGPU_WPR_OFFSET;
+        inf->size = DGPU_WPR_SIZE;
+}
+
+static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value)
+{
+        dma_addr->lo |= u64_lo32(value);
+        dma_addr->hi |= u64_hi32(value);
+}
+
+static int gp106_alloc_blob_space(struct gk20a *g,
+                size_t size, struct mem_desc *mem)
+{
+        struct wpr_carveout_info wpr_inf;
+        int err;
+
+        if (mem->size)
+                return 0;
+
+        g->ops.pmu.get_wpr(g, &wpr_inf);
+
+        /*
+         * Even though this mem_desc wouldn't be used, the wpr region needs to
+         * be reserved in the allocator.
+         */
+        err = gk20a_gmmu_alloc_attr_vid_at(g, 0, wpr_inf.size,
+                                &g->acr.wpr_dummy, wpr_inf.wpr_base);
+        if (err)
+                return err;
+
+        return gk20a_gmmu_alloc_attr_vid_at(g, 0, wpr_inf.size, mem,
+                        wpr_inf.nonwpr_base);
+}
+
+void gp106_init_secure_pmu(struct gpu_ops *gops)
+{
+        gops->pmu.prepare_ucode = gp106_prepare_ucode_blob;
+        gops->pmu.pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn;
+        gops->pmu.is_lazy_bootstrap = gm206_is_lazy_bootstrap;
+        gops->pmu.is_priv_load = gm206_is_priv_load;
+        gops->pmu.get_wpr = gp106_wpr_info;
+        gops->pmu.alloc_blob_space = gp106_alloc_blob_space;
+        gops->pmu.pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg;
+        gops->pmu.flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc;
+        gops->pmu.falcon_wait_for_halt = sec2_wait_for_halt;
+        gops->pmu.falcon_clear_halt_interrupt_status =
+                        sec2_clear_halt_interrupt_status;
+        gops->pmu.init_falcon_setup_hw = init_sec2_setup_hw1;
+}
+/* TODO - check if any free blob res needed*/
+
+static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
+{
+        const struct firmware *pmu_fw, *pmu_desc, *pmu_sig;
+        struct pmu_gk20a *pmu = &g->pmu;
+        struct lsf_ucode_desc_v1 *lsf_desc;
+        int err;
+
+        gp106_dbg_pmu("requesting PMU ucode in gp106\n");
+        pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE,
+                                        NVGPU_REQUEST_FIRMWARE_NO_SOC);
+        if (!pmu_fw) {
+                gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode!!");
+                return -ENOENT;
+        }
+        g->acr.pmu_fw = pmu_fw;
+        gp106_dbg_pmu("Loaded PMU ucode in for blob preparation");
+
+        gp106_dbg_pmu("requesting PMU ucode desc in GM20B\n");
+        pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC,
+                                        NVGPU_REQUEST_FIRMWARE_NO_SOC);
+        if (!pmu_desc) {
+                gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!");
+                err = -ENOENT;
+                goto release_img_fw;
+        }
+        pmu_sig = nvgpu_request_firmware(g, GM20B_PMU_UCODE_SIG,
+                                        NVGPU_REQUEST_FIRMWARE_NO_SOC);
+        if (!pmu_sig) {
+                gk20a_err(dev_from_gk20a(g), "failed to load pmu sig!!");
+                err = -ENOENT;
+                goto release_desc;
+        }
+        pmu->desc_v1 = (struct pmu_ucode_desc_v1 *)pmu_desc->data;
+        pmu->ucode_image = (u32 *)pmu_fw->data;
+        g->acr.pmu_desc = pmu_desc;
+
+        err = gk20a_init_pmu(pmu);
+        if (err) {
+                gp106_dbg_pmu("failed to set function pointers\n");
+                goto release_sig;
+        }
+
+        lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc_v1), GFP_KERNEL);
+        if (!lsf_desc) {
+                err = -ENOMEM;
+                goto release_sig;
+        }
+        memcpy(lsf_desc, (void *)pmu_sig->data, sizeof(struct lsf_ucode_desc_v1));
+        lsf_desc->falcon_id = LSF_FALCON_ID_PMU;
+
+        p_img->desc = pmu->desc_v1;
+        p_img->data = pmu->ucode_image;
+        p_img->data_size = pmu->desc_v1->app_start_offset
+                                                + pmu->desc_v1->app_size;
+        p_img->fw_ver = NULL;
+        p_img->header = NULL;
+        p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
+        gp106_dbg_pmu("requesting PMU ucode in GM20B exit\n");
+
+        release_firmware(pmu_sig);
+        return 0;
+release_sig:
+        release_firmware(pmu_sig);
+release_desc:
+        release_firmware(pmu_desc);
+release_img_fw:
+        release_firmware(pmu_fw);
+        return err;
+}
+
+static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
+{
+        u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
+        struct lsf_ucode_desc_v1 *lsf_desc;
+        const struct firmware *fecs_sig = NULL;
+        int err;
+
+        switch (ver) {
+                case NVGPU_GPUID_GP104:
+                        fecs_sig = nvgpu_request_firmware(g,
+                                        GP104_FECS_UCODE_SIG,
+                                        NVGPU_REQUEST_FIRMWARE_NO_SOC);
+                        break;
+                case NVGPU_GPUID_GP106:
+                        fecs_sig = nvgpu_request_firmware(g,
+                                        GP106_FECS_UCODE_SIG,
+                                        NVGPU_REQUEST_FIRMWARE_NO_SOC);
+                        break;
+                default:
+                        gk20a_err(g->dev, "no support for GPUID %x", ver);
+        }
+
+        if (!fecs_sig) {
+                gk20a_err(dev_from_gk20a(g), "failed to load fecs sig");
+                return -ENOENT;
+        }
+        lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc_v1), GFP_KERNEL);
+        if (!lsf_desc) {
+                err = -ENOMEM;
+                goto rel_sig;
+        }
+        memcpy(lsf_desc, (void *)fecs_sig->data, sizeof(struct lsf_ucode_desc_v1));
+        lsf_desc->falcon_id = LSF_FALCON_ID_FECS;
+
+        p_img->desc = kzalloc(sizeof(struct pmu_ucode_desc_v1), GFP_KERNEL);
+        if (p_img->desc == NULL) {
+                err = -ENOMEM;
+                goto free_lsf_desc;
+        }
+
+        p_img->desc->bootloader_start_offset =
+                g->ctxsw_ucode_info.fecs.boot.offset;
+        p_img->desc->bootloader_size =
+                ALIGN(g->ctxsw_ucode_info.fecs.boot.size, 256);
+        p_img->desc->bootloader_imem_offset =
+                g->ctxsw_ucode_info.fecs.boot_imem_offset;
+        p_img->desc->bootloader_entry_point =
+                g->ctxsw_ucode_info.fecs.boot_entry;
+
+        p_img->desc->image_size =
+                ALIGN(g->ctxsw_ucode_info.fecs.boot.size, 256) +
+                ALIGN(g->ctxsw_ucode_info.fecs.code.size, 256) +
+                ALIGN(g->ctxsw_ucode_info.fecs.data.size, 256);
+        p_img->desc->app_size = ALIGN(g->ctxsw_ucode_info.fecs.code.size, 256) +
+                ALIGN(g->ctxsw_ucode_info.fecs.data.size, 256);
+        p_img->desc->app_start_offset = g->ctxsw_ucode_info.fecs.code.offset;
+        p_img->desc->app_imem_offset = 0;
+        p_img->desc->app_imem_entry = 0;
+        p_img->desc->app_dmem_offset = 0;
+        p_img->desc->app_resident_code_offset = 0;
+        p_img->desc->app_resident_code_size =
+                g->ctxsw_ucode_info.fecs.code.size;
+        p_img->desc->app_resident_data_offset =
+                g->ctxsw_ucode_info.fecs.data.offset -
+                g->ctxsw_ucode_info.fecs.code.offset;
+        p_img->desc->app_resident_data_size =
+                g->ctxsw_ucode_info.fecs.data.size;
+        p_img->data = g->ctxsw_ucode_info.surface_desc.cpu_va;
+        p_img->data_size = p_img->desc->image_size;
+
+        p_img->fw_ver = NULL;
+        p_img->header = NULL;
+        p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
+        gp106_dbg_pmu("fecs fw loaded\n");
+        release_firmware(fecs_sig);
+        return 0;
+free_lsf_desc:
+        kfree(lsf_desc);
+rel_sig:
+        release_firmware(fecs_sig);
+        return err;
+}
+
+static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
+{
+        u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
+        struct lsf_ucode_desc_v1 *lsf_desc;
+        const struct firmware *gpccs_sig = NULL;
+        int err;
+
+        if (g->ops.securegpccs == false)
+                return -ENOENT;
+
+        switch (ver) {
+                case NVGPU_GPUID_GP104:
+                        gpccs_sig = nvgpu_request_firmware(g,
+                                        GP104_GPCCS_UCODE_SIG,
+                                        NVGPU_REQUEST_FIRMWARE_NO_SOC);
+                        break;
+                case NVGPU_GPUID_GP106:
+                        gpccs_sig = nvgpu_request_firmware(g,
+                                        GP106_GPCCS_UCODE_SIG,
+                                        NVGPU_REQUEST_FIRMWARE_NO_SOC);
+                        break;
+                default:
+                        gk20a_err(g->dev, "no support for GPUID %x", ver);
+        }
+
+        if (!gpccs_sig) {
+                gk20a_err(dev_from_gk20a(g), "failed to load gpccs sig");
+                return -ENOENT;
+        }
+        lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc_v1), GFP_KERNEL);
+        if (!lsf_desc) {
+                err = -ENOMEM;
+                goto rel_sig;
+        }
+        memcpy(lsf_desc, (void *)gpccs_sig->data,
+                sizeof(struct lsf_ucode_desc_v1));
+        lsf_desc->falcon_id = LSF_FALCON_ID_GPCCS;
+
+        p_img->desc = kzalloc(sizeof(struct pmu_ucode_desc_v1), GFP_KERNEL);
+        if (p_img->desc == NULL) {
+                err = -ENOMEM;
+                goto free_lsf_desc;
+        }
+
+        p_img->desc->bootloader_start_offset =
+                0;
+        p_img->desc->bootloader_size =
+                ALIGN(g->ctxsw_ucode_info.gpccs.boot.size, 256);
+        p_img->desc->bootloader_imem_offset =
+                g->ctxsw_ucode_info.gpccs.boot_imem_offset;
+        p_img->desc->bootloader_entry_point =
+                g->ctxsw_ucode_info.gpccs.boot_entry;
+
+        p_img->desc->image_size =
+                ALIGN(g->ctxsw_ucode_info.gpccs.boot.size, 256) +
+                ALIGN(g->ctxsw_ucode_info.gpccs.code.size, 256) +
+                ALIGN(g->ctxsw_ucode_info.gpccs.data.size, 256);
+        p_img->desc->app_size = ALIGN(g->ctxsw_ucode_info.gpccs.code.size, 256)
+                + ALIGN(g->ctxsw_ucode_info.gpccs.data.size, 256);
+        p_img->desc->app_start_offset = p_img->desc->bootloader_size;
+        p_img->desc->app_imem_offset = 0;
+        p_img->desc->app_imem_entry = 0;
+        p_img->desc->app_dmem_offset = 0;
+        p_img->desc->app_resident_code_offset = 0;
+        p_img->desc->app_resident_code_size =
+                ALIGN(g->ctxsw_ucode_info.gpccs.code.size, 256);
+        p_img->desc->app_resident_data_offset =
+                ALIGN(g->ctxsw_ucode_info.gpccs.data.offset, 256) -
+                ALIGN(g->ctxsw_ucode_info.gpccs.code.offset, 256);
+        p_img->desc->app_resident_data_size =
+                ALIGN(g->ctxsw_ucode_info.gpccs.data.size, 256);
+        p_img->data = (u32 *)((u8 *)g->ctxsw_ucode_info.surface_desc.cpu_va +
+                g->ctxsw_ucode_info.gpccs.boot.offset);
+        p_img->data_size = ALIGN(p_img->desc->image_size, 256);
+        p_img->fw_ver = NULL;
+        p_img->header = NULL;
+        p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
+        gp106_dbg_pmu("gpccs fw loaded\n");
+        release_firmware(gpccs_sig);
+        return 0;
+free_lsf_desc:
+        kfree(lsf_desc);
+rel_sig:
+        release_firmware(gpccs_sig);
+        return err;
+}
+
+static int gp106_prepare_ucode_blob(struct gk20a *g)
+{
+
+        int err;
+        struct ls_flcn_mgr_v1 lsfm_l, *plsfm;
+        struct pmu_gk20a *pmu = &g->pmu;
+        struct wpr_carveout_info wpr_inf;
+
+        if (g->acr.ucode_blob.cpu_va) {
+                /*Recovery case, we do not need to form
+                non WPR blob of ucodes*/
+                err = gk20a_init_pmu(pmu);
+                if (err) {
+                        gp106_dbg_pmu("failed to set function pointers\n");
+                        return err;
+                }
+                return 0;
+        }
+        plsfm = &lsfm_l;
+        memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1));
+        gp106_dbg_pmu("fetching GMMU regs\n");
+        gm20b_mm_mmu_vpr_info_fetch(g);
+        gr_gk20a_init_ctxsw_ucode(g);
+
+        g->ops.pmu.get_wpr(g, &wpr_inf);
+        gp106_dbg_pmu("wpr carveout base:%llx\n", (wpr_inf.wpr_base));
+        gp106_dbg_pmu("wpr carveout size :%x\n", (u32)wpr_inf.size);
+
+        /* Discover all managed falcons*/
+        err = lsfm_discover_ucode_images(g, plsfm);
+        gp106_dbg_pmu(" Managed Falcon cnt %d\n", plsfm->managed_flcn_cnt);
+        if (err)
+                goto exit_err;
+
+        if (plsfm->managed_flcn_cnt && !g->acr.ucode_blob.cpu_va) {
+                /* Generate WPR requirements*/
+                err = lsf_gen_wpr_requirements(g, plsfm);
+                if (err)
+                        goto exit_err;
+
+                /*Alloc memory to hold ucode blob contents*/
+                err = g->ops.pmu.alloc_blob_space(g, plsfm->wpr_size
+                                                        ,&g->acr.ucode_blob);
+                if (err)
+                        goto exit_err;
+
+                gp106_dbg_pmu("managed LS falcon %d, WPR size %d bytes.\n",
+                        plsfm->managed_flcn_cnt, plsfm->wpr_size);
+
+                lsfm_init_wpr_contents(g, plsfm, &g->acr.ucode_blob);
+        } else {
+                gp106_dbg_pmu("LSFM is managing no falcons.\n");
+        }
+        gp106_dbg_pmu("prepare ucode blob return 0\n");
+        free_acr_resources(g, plsfm);
+
+ exit_err:
+        return err;
+}
+
+static u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
+        u32 falcon_id)
+{
+        return (plsfm->disable_mask >> falcon_id) & 0x1;
+}
+
+/* Discover all managed falcon ucode images */
+static int lsfm_discover_ucode_images(struct gk20a *g,
+        struct ls_flcn_mgr_v1 *plsfm)
+{
+        struct pmu_gk20a *pmu = &g->pmu;
+        struct flcn_ucode_img_v1 ucode_img;
+        u32 falcon_id;
+        u32 i;
+        int status;
+
+        /* LSFM requires a secure PMU, discover it first.*/
+        /* Obtain the PMU ucode image and add it to the list if required*/
+        memset(&ucode_img, 0, sizeof(ucode_img));
+        status = pmu_ucode_details(g, &ucode_img);
+        if (status == 0) {
+                if (ucode_img.lsf_desc != NULL) {
+                        /* The falon_id is formed by grabbing the static base
+                         * falon_id from the image and adding the
+                         * engine-designated falcon instance.*/
+                        pmu->pmu_mode |= PMU_SECURE_MODE;
+                        falcon_id = ucode_img.lsf_desc->falcon_id +
+                                ucode_img.flcn_inst;
+
+                        if (!lsfm_falcon_disabled(g, plsfm, falcon_id)) {
+                                pmu->falcon_id = falcon_id;
+                                if (lsfm_add_ucode_img(g, plsfm, &ucode_img,
+                                        pmu->falcon_id) == 0)
+                                        pmu->pmu_mode |= PMU_LSFM_MANAGED;
+
+                                plsfm->managed_flcn_cnt++;
+                        } else {
+                                gp106_dbg_pmu("id not managed %d\n",
+                                        ucode_img.lsf_desc->falcon_id);
+                        }
+                }
+
+                /*Free any ucode image resources if not managing this falcon*/
+                if (!(pmu->pmu_mode & PMU_LSFM_MANAGED)) {
+                        gp106_dbg_pmu("pmu is not LSFM managed\n");
+                        lsfm_free_ucode_img_res(&ucode_img);
+                }
+        }
+
+        /* Enumerate all constructed falcon objects,
+         as we need the ucode image info and total falcon count.*/
+
+        /*0th index is always PMU which is already handled in earlier
+        if condition*/
+        for (i = 1; i < (MAX_SUPPORTED_LSFM); i++) {
+                memset(&ucode_img, 0, sizeof(ucode_img));
+                if (pmu_acr_supp_ucode_list[i](g, &ucode_img) == 0) {
+                        if (ucode_img.lsf_desc != NULL) {
+                                /* We have engine sigs, ensure that this falcon
+                                is aware of the secure mode expectations
+                                (ACR status)*/
+
+                                /* falon_id is formed by grabbing the static
+                                base falonId from the image and adding the
+                                engine-designated falcon instance. */
+                                falcon_id = ucode_img.lsf_desc->falcon_id +
+                                        ucode_img.flcn_inst;
+
+                                if (!lsfm_falcon_disabled(g, plsfm,
+                                        falcon_id)) {
+                                        /* Do not manage non-FB ucode*/
+                                        if (lsfm_add_ucode_img(g,
+                                                plsfm, &ucode_img, falcon_id)
+                                                == 0)
+                                                plsfm->managed_flcn_cnt++;
+                                } else {
+                                        gp106_dbg_pmu("not managed %d\n",
+                                                ucode_img.lsf_desc->falcon_id);
+                                        lsfm_free_nonpmu_ucode_img_res(
+                                                &ucode_img);
+                                }
+                        }
+                } else {
+                        /* Consumed all available falcon objects */
+                        gp106_dbg_pmu("Done checking for ucodes %d\n", i);
+                        break;
+                }
+        }
+        return 0;
+}
+
+static int gp106_pmu_populate_loader_cfg(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size)
+{
+        struct wpr_carveout_info wpr_inf;
+        struct pmu_gk20a *pmu = &g->pmu;
+        struct lsfm_managed_ucode_img_v2 *p_lsfm =
+                (struct lsfm_managed_ucode_img_v2 *)lsfm;
+        struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img);
+        struct flcn_bl_dmem_desc_v1 *ldr_cfg =
+                                &(p_lsfm->bl_gen_desc.bl_dmem_desc_v1);
+        u64 addr_base;
+        struct pmu_ucode_desc_v1 *desc;
+        u64 addr_code, addr_data;
+        u32 addr_args;
+
+        if (p_img->desc == NULL) /*This means its a header based ucode,
+                                  and so we do not fill BL gen desc structure*/
+                return -EINVAL;
+        desc = p_img->desc;
+        /*
+         Calculate physical and virtual addresses for various portions of
+         the PMU ucode image
+         Calculate the 32-bit addresses for the application code, application
+         data, and bootloader code. These values are all based on IM_BASE.
+         The 32-bit addresses will be the upper 32-bits of the virtual or
+         physical addresses of each respective segment.
+        */
+        addr_base = p_lsfm->lsb_header.ucode_off;
+        g->ops.pmu.get_wpr(g, &wpr_inf);
+        addr_base += (wpr_inf.wpr_base);
+
+        gp106_dbg_pmu("pmu loader cfg u32 addrbase %x\n", (u32)addr_base);
+        /*From linux*/
+        addr_code = u64_lo32((addr_base +
+                                desc->app_start_offset +
+                                desc->app_resident_code_offset) );
+        gp106_dbg_pmu("app start %d app res code off %d\n",
+                desc->app_start_offset, desc->app_resident_code_offset);
+        addr_data = u64_lo32((addr_base +
+                                desc->app_start_offset +
+                                desc->app_resident_data_offset) );
+        gp106_dbg_pmu("app res data offset%d\n",
+                desc->app_resident_data_offset);
+        gp106_dbg_pmu("bl start off %d\n", desc->bootloader_start_offset);
+
+        addr_args = ((pwr_falcon_hwcfg_dmem_size_v(
+                        gk20a_readl(g, pwr_falcon_hwcfg_r())))
+                        << GK20A_PMU_DMEM_BLKSIZE2);
+
+        addr_args -= g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu);
+
+        gp106_dbg_pmu("addr_args %x\n", addr_args);
+
+        /* Populate the LOADER_CONFIG state */
+        memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc_v1));
+        ldr_cfg->ctx_dma = GK20A_PMU_DMAIDX_UCODE;
+        flcn64_set_dma(&ldr_cfg->code_dma_base, addr_code);
+        ldr_cfg->non_sec_code_off = desc->app_resident_code_offset;
+        ldr_cfg->non_sec_code_size = desc->app_resident_code_size;
+        flcn64_set_dma(&ldr_cfg->data_dma_base, addr_data);
+        ldr_cfg->data_size = desc->app_resident_data_size;
+        ldr_cfg->code_entry_point = desc->app_imem_entry;
+
+        /* Update the argc/argv members*/
+        ldr_cfg->argc = 1;
+        ldr_cfg->argv = addr_args;
+
+        *p_bl_gen_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
+
+        g->acr.pmu_args = addr_args;
+        return 0;
+}
+
+static int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid)
+{
+        struct wpr_carveout_info wpr_inf;
+        struct lsfm_managed_ucode_img_v2 *p_lsfm =
+                        (struct lsfm_managed_ucode_img_v2 *)lsfm;
+        struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img);
+        struct flcn_bl_dmem_desc_v1 *ldr_cfg =
+                        &(p_lsfm->bl_gen_desc.bl_dmem_desc_v1);
+        u64 addr_base;
+        struct pmu_ucode_desc_v1 *desc;
+        u64 addr_code, addr_data;
+
+        if (p_img->desc == NULL) /*This means its a header based ucode,
+                                  and so we do not fill BL gen desc structure*/
+                return -EINVAL;
+        desc = p_img->desc;
+
+        /*
+         Calculate physical and virtual addresses for various portions of
+         the PMU ucode image
+         Calculate the 32-bit addresses for the application code, application
+         data, and bootloader code. These values are all based on IM_BASE.
+         The 32-bit addresses will be the upper 32-bits of the virtual or
+         physical addresses of each respective segment.
+        */
+        addr_base = p_lsfm->lsb_header.ucode_off;
+        g->ops.pmu.get_wpr(g, &wpr_inf);
+        addr_base += (wpr_inf.wpr_base);
+
+        gp106_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base,
+                        p_lsfm->wpr_header.falcon_id);
+        addr_code = u64_lo32((addr_base +
+                                desc->app_start_offset +
+                                desc->app_resident_code_offset) );
+        addr_data = u64_lo32((addr_base +
+                                desc->app_start_offset +
+                                desc->app_resident_data_offset) );
+
+        gp106_dbg_pmu("gen cfg %x u32 addrcode %x & data %x load offset %xID\n",
+                        (u32)addr_code, (u32)addr_data, desc->bootloader_start_offset,
+                        p_lsfm->wpr_header.falcon_id);
+
+        /* Populate the LOADER_CONFIG state */
+        memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc_v1));
+        ldr_cfg->ctx_dma = GK20A_PMU_DMAIDX_UCODE;
+        flcn64_set_dma(&ldr_cfg->code_dma_base, addr_code);
+        ldr_cfg->non_sec_code_size = desc->app_resident_code_size;
+        flcn64_set_dma(&ldr_cfg->data_dma_base, addr_data);
+        ldr_cfg->data_size = desc->app_resident_data_size;
+        ldr_cfg->code_entry_point = desc->app_imem_entry;
+
+        *p_bl_gen_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
+        return 0;
+}
+
+/* Populate falcon boot loader generic desc.*/
+static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
+                struct lsfm_managed_ucode_img_v2 *pnode)
+{
+
+        struct pmu_gk20a *pmu = &g->pmu;
+        if (pnode->wpr_header.falcon_id != pmu->falcon_id) {
+                gp106_dbg_pmu("non pmu. write flcn bl gen desc\n");
+                g->ops.pmu.flcn_populate_bl_dmem_desc(g,
+                                pnode, &pnode->bl_gen_desc_size,
+                                        pnode->wpr_header.falcon_id);
+                return 0;
+        }
+
+        if (pmu->pmu_mode & PMU_LSFM_MANAGED) {
+                gp106_dbg_pmu("pmu write flcn bl gen desc\n");
+                if (pnode->wpr_header.falcon_id == pmu->falcon_id)
+                        return g->ops.pmu.pmu_populate_loader_cfg(g, pnode,
+                                &pnode->bl_gen_desc_size);
+        }
+
+        /* Failed to find the falcon requested. */
+        return -ENOENT;
+}
+
+/* Initialize WPR contents */
+static void lsfm_init_wpr_contents(struct gk20a *g,
+                struct ls_flcn_mgr_v1 *plsfm, struct mem_desc *ucode)
+{
+        struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list;
+        u32 i;
+
+        /* The WPR array is at the base of the WPR */
+        pnode = plsfm->ucode_img_list;
+        i = 0;
+
+        /*
+         * Walk the managed falcons, flush WPR and LSB headers to FB.
+         * flush any bl args to the storage area relative to the
+         * ucode image (appended on the end as a DMEM area).
+         */
+        while (pnode) {
+                /* Flush WPR header to memory*/
+                gk20a_mem_wr_n(g, ucode, i * sizeof(pnode->wpr_header),
+                                &pnode->wpr_header, sizeof(pnode->wpr_header));
+
+                gp106_dbg_pmu("wpr header");
+                gp106_dbg_pmu("falconid :%d",
+                                pnode->wpr_header.falcon_id);
+                gp106_dbg_pmu("lsb_offset :%x",
+                                pnode->wpr_header.lsb_offset);
+                gp106_dbg_pmu("bootstrap_owner :%d",
+                        pnode->wpr_header.bootstrap_owner);
+                gp106_dbg_pmu("lazy_bootstrap :%d",
+                                pnode->wpr_header.lazy_bootstrap);
+                gp106_dbg_pmu("status :%d",
+                                pnode->wpr_header.status);
+
+                /*Flush LSB header to memory*/
+                gk20a_mem_wr_n(g, ucode, pnode->wpr_header.lsb_offset,
+                                &pnode->lsb_header, sizeof(pnode->lsb_header));
+
+                gp106_dbg_pmu("lsb header");
+                gp106_dbg_pmu("ucode_off :%x",
+                                pnode->lsb_header.ucode_off);
+                gp106_dbg_pmu("ucode_size :%x",
+                                pnode->lsb_header.ucode_size);
+                gp106_dbg_pmu("data_size :%x",
+                                pnode->lsb_header.data_size);
+                gp106_dbg_pmu("bl_code_size :%x",
+                                pnode->lsb_header.bl_code_size);
+                gp106_dbg_pmu("bl_imem_off :%x",
+                                pnode->lsb_header.bl_imem_off);
+                gp106_dbg_pmu("bl_data_off :%x",
+                                pnode->lsb_header.bl_data_off);
+                gp106_dbg_pmu("bl_data_size :%x",
+                                pnode->lsb_header.bl_data_size);
+                gp106_dbg_pmu("app_code_off :%x",
+                                pnode->lsb_header.app_code_off);
+                gp106_dbg_pmu("app_code_size :%x",
+                                pnode->lsb_header.app_code_size);
+                gp106_dbg_pmu("app_data_off :%x",
+                                pnode->lsb_header.app_data_off);
+                gp106_dbg_pmu("app_data_size :%x",
+                                pnode->lsb_header.app_data_size);
+                gp106_dbg_pmu("flags :%x",
+                                pnode->lsb_header.flags);
+
+                /*If this falcon has a boot loader and related args,
+                 * flush them.*/
+                if (!pnode->ucode_img.header) {
+                        /*Populate gen bl and flush to memory*/
+                        lsfm_fill_flcn_bl_gen_desc(g, pnode);
+                        gk20a_mem_wr_n(g, ucode,
+                                        pnode->lsb_header.bl_data_off,
+                                        &pnode->bl_gen_desc,
+                                        pnode->bl_gen_desc_size);
+                }
+                /*Copying of ucode*/
+                gk20a_mem_wr_n(g, ucode, pnode->lsb_header.ucode_off,
+                                pnode->ucode_img.data,
+                                pnode->ucode_img.data_size);
+                pnode = pnode->next;
+                i++;
+        }
+
+        /* Tag the terminator WPR header with an invalid falcon ID. */
+        gk20a_mem_wr32(g, ucode,
+                        plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header) +
+                        offsetof(struct lsf_wpr_header, falcon_id),
+                        LSF_FALCON_ID_INVALID);
+}
+
+/*!
+ * lsfm_parse_no_loader_ucode: parses UCODE header of falcon
+ *
+ * @param[in] p_ucodehdr : UCODE header
+ * @param[out] lsb_hdr : updates values in LSB header
+ *
+ * @return 0
+ */
+static int lsfm_parse_no_loader_ucode(u32 *p_ucodehdr,
+        struct lsf_lsb_header_v1 *lsb_hdr)
+{
+
+        u32 code_size = 0;
+        u32 data_size = 0;
+        u32 i = 0;
+        u32 total_apps = p_ucodehdr[FLCN_NL_UCODE_HDR_NUM_APPS_IND];
+
+        /* Lets calculate code size*/
+        code_size += p_ucodehdr[FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND];
+        for (i = 0; i < total_apps; i++) {
+                code_size += p_ucodehdr[FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND
+                        (total_apps, i)];
+        }
+        code_size += p_ucodehdr[FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(total_apps)];
+
+        /* Calculate data size*/
+        data_size += p_ucodehdr[FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND];
+        for (i = 0; i < total_apps; i++) {
+                data_size += p_ucodehdr[FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND
+                        (total_apps, i)];
+        }
+
+        lsb_hdr->ucode_size = code_size;
+        lsb_hdr->data_size = data_size;
+        lsb_hdr->bl_code_size = p_ucodehdr[FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND];
+        lsb_hdr->bl_imem_off = 0;
+        lsb_hdr->bl_data_off = p_ucodehdr[FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND];
+        lsb_hdr->bl_data_size = p_ucodehdr[FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND];
+        return 0;
+}
+
+/*!
+ * @brief lsfm_fill_static_lsb_hdr_info
+ * Populate static LSB header infomation using the provided ucode image
+ */
+static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
+        u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode)
+{
+
+        struct pmu_gk20a *pmu = &g->pmu;
+        u32 full_app_size = 0;
+        u32 data = 0;
+
+        if (pnode->ucode_img.lsf_desc)
+                memcpy(&pnode->lsb_header.signature, pnode->ucode_img.lsf_desc,
+                        sizeof(struct lsf_ucode_desc_v1));
+        pnode->lsb_header.ucode_size = pnode->ucode_img.data_size;
+
+        /* The remainder of the LSB depends on the loader usage */
+        if (pnode->ucode_img.header) {
+                /* Does not use a loader */
+                pnode->lsb_header.data_size = 0;
+                pnode->lsb_header.bl_code_size = 0;
+                pnode->lsb_header.bl_data_off = 0;
+                pnode->lsb_header.bl_data_size = 0;
+
+                lsfm_parse_no_loader_ucode(pnode->ucode_img.header,
+                        &(pnode->lsb_header));
+
+                /* Load the first 256 bytes of IMEM. */
+                /* Set LOAD_CODE_AT_0 and DMACTL_REQ_CTX.
+                True for all method based falcons */
+                data = NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE |
+                        NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE;
+                pnode->lsb_header.flags = data;
+        } else {
+                /* Uses a loader. that is has a desc */
+                pnode->lsb_header.data_size = 0;
+
+                /* The loader code size is already aligned (padded) such that
+                the code following it is aligned, but the size in the image
+                desc is not, bloat it up to be on a 256 byte alignment. */
+                pnode->lsb_header.bl_code_size = ALIGN(
+                        pnode->ucode_img.desc->bootloader_size,
+                        LSF_BL_CODE_SIZE_ALIGNMENT);
+                full_app_size = ALIGN(pnode->ucode_img.desc->app_size,
+                        LSF_BL_CODE_SIZE_ALIGNMENT) +
+                        pnode->lsb_header.bl_code_size;
+                pnode->lsb_header.ucode_size = ALIGN(
+                        pnode->ucode_img.desc->app_resident_data_offset,
+                        LSF_BL_CODE_SIZE_ALIGNMENT) +
+                        pnode->lsb_header.bl_code_size;
+                pnode->lsb_header.data_size = full_app_size -
+                        pnode->lsb_header.ucode_size;
+                /* Though the BL is located at 0th offset of the image, the VA
+                is different to make sure that it doesnt collide the actual OS
+                VA range */
+                pnode->lsb_header.bl_imem_off =
+                        pnode->ucode_img.desc->bootloader_imem_offset;
+
+                /* TODO: OBJFLCN should export properties using which the below
+                        flags should be populated.*/
+                pnode->lsb_header.flags = 0;
+
+                if (falcon_id == pmu->falcon_id) {
+                        data = NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE;
+                        pnode->lsb_header.flags = data;
+                }
+
+                if(g->ops.pmu.is_priv_load(falcon_id))
+                        pnode->lsb_header.flags |=
+                                NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE;
+        }
+}
+
+/* Adds a ucode image to the list of managed ucode images managed. */
+static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
+        struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id)
+{
+        struct lsfm_managed_ucode_img_v2 *pnode;
+
+        pnode = kzalloc(sizeof(struct lsfm_managed_ucode_img_v2), GFP_KERNEL);
+        if (pnode == NULL)
+                return -ENOMEM;
+
+        /* Keep a copy of the ucode image info locally */
+        memcpy(&pnode->ucode_img, ucode_image, sizeof(struct flcn_ucode_img_v1));
+
+        /* Fill in static WPR header info*/
+        pnode->wpr_header.falcon_id = falcon_id;
+        pnode->wpr_header.bootstrap_owner = 0x07; //LSF_BOOTSTRAP_OWNER_DEFAULT;
+        pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY;
+
+        pnode->wpr_header.lazy_bootstrap =
+                        g->ops.pmu.is_lazy_bootstrap(falcon_id);
+
+        /*TODO to check if PDB_PROP_FLCN_LAZY_BOOTSTRAP is to be supported by
+        Android */
+        /* Fill in static LSB header info elsewhere */
+        lsfm_fill_static_lsb_hdr_info(g, falcon_id, pnode);
+        pnode->wpr_header.bin_version = pnode->lsb_header.signature.version;
+        pnode->next = plsfm->ucode_img_list;
+        plsfm->ucode_img_list = pnode;
+        return 0;
+}
+
+/* Free any ucode image structure resources*/
+static void lsfm_free_ucode_img_res(struct flcn_ucode_img_v1 *p_img)
+{
+        if (p_img->lsf_desc != NULL) {
+                kfree(p_img->lsf_desc);
+                p_img->lsf_desc = NULL;
+        }
+}
+
+/* Free any ucode image structure resources*/
+static void lsfm_free_nonpmu_ucode_img_res(struct flcn_ucode_img_v1 *p_img)
+{
+        if (p_img->lsf_desc != NULL) {
+                kfree(p_img->lsf_desc);
+                p_img->lsf_desc = NULL;
+        }
+        if (p_img->desc != NULL) {
+                kfree(p_img->desc);
+                p_img->desc = NULL;
+        }
+}
+
+static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm)
+{
+        u32 cnt = plsfm->managed_flcn_cnt;
+        struct lsfm_managed_ucode_img_v2 *mg_ucode_img;
+
+        while (cnt) {
+                mg_ucode_img = plsfm->ucode_img_list;
+                if (mg_ucode_img->ucode_img.lsf_desc->falcon_id ==
+                                LSF_FALCON_ID_PMU)
+                        lsfm_free_ucode_img_res(&mg_ucode_img->ucode_img);
+                else
+                        lsfm_free_nonpmu_ucode_img_res(
+                                &mg_ucode_img->ucode_img);
+                plsfm->ucode_img_list = mg_ucode_img->next;
+                kfree(mg_ucode_img);
+                cnt--;
+        }
+}
+
+/* Generate WPR requirements for ACR allocation request */
+static int lsf_gen_wpr_requirements(struct gk20a *g,
+                struct ls_flcn_mgr_v1 *plsfm)
+{
+        struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list;
+        u32 wpr_offset;
+
+        /* Calculate WPR size required */
+
+        /* Start with an array of WPR headers at the base of the WPR.
+         The expectation here is that the secure falcon will do a single DMA
+         read of this array and cache it internally so it's OK to pack these.
+         Also, we add 1 to the falcon count to indicate the end of the array.*/
+        wpr_offset = sizeof(struct lsf_wpr_header_v1) *
+                (plsfm->managed_flcn_cnt+1);
+
+        /* Walk the managed falcons, accounting for the LSB structs
+        as well as the ucode images. */
+        while (pnode) {
+                /* Align, save off, and include an LSB header size */
+                wpr_offset = ALIGN(wpr_offset,
+                        LSF_LSB_HEADER_ALIGNMENT);
+                pnode->wpr_header.lsb_offset = wpr_offset;
+                wpr_offset += sizeof(struct lsf_lsb_header_v1);
+
+                /* Align, save off, and include the original (static)
+                ucode image size */
+                wpr_offset = ALIGN(wpr_offset,
+                        LSF_UCODE_DATA_ALIGNMENT);
+                pnode->lsb_header.ucode_off = wpr_offset;
+                wpr_offset += pnode->ucode_img.data_size;
+
+                /* For falcons that use a boot loader (BL), we append a loader
+                desc structure on the end of the ucode image and consider this
+                the boot loader data. The host will then copy the loader desc
+                args to this space within the WPR region (before locking down)
+                and the HS bin will then copy them to DMEM 0 for the loader. */
+                if (!pnode->ucode_img.header) {
+                        /* Track the size for LSB details filled in later
+                         Note that at this point we don't know what kind of i
+                        boot loader desc, so we just take the size of the
+                        generic one, which is the largest it will will ever be.
+                        */
+                        /* Align (size bloat) and save off generic
+                        descriptor size*/
+                        pnode->lsb_header.bl_data_size = ALIGN(
+                                sizeof(pnode->bl_gen_desc),
+                                LSF_BL_DATA_SIZE_ALIGNMENT);
+
+                        /*Align, save off, and include the additional BL data*/
+                        wpr_offset = ALIGN(wpr_offset,
+                                LSF_BL_DATA_ALIGNMENT);
+                        pnode->lsb_header.bl_data_off = wpr_offset;
+                        wpr_offset += pnode->lsb_header.bl_data_size;
+                } else {
+                        /* bl_data_off is already assigned in static
+                        information. But that is from start of the image */
+                        pnode->lsb_header.bl_data_off +=
+                                (wpr_offset - pnode->ucode_img.data_size);
+                }
+
+                /* Finally, update ucode surface size to include updates */
+                pnode->full_ucode_size = wpr_offset -
+                        pnode->lsb_header.ucode_off;
+                if (pnode->wpr_header.falcon_id != LSF_FALCON_ID_PMU) {
+                        pnode->lsb_header.app_code_off =
+                                pnode->lsb_header.bl_code_size;
+                        pnode->lsb_header.app_code_size =
+                                pnode->lsb_header.ucode_size -
+                                pnode->lsb_header.bl_code_size;
+                        pnode->lsb_header.app_data_off =
+                                pnode->lsb_header.ucode_size;
+                        pnode->lsb_header.app_data_size =
+                                pnode->lsb_header.data_size;
+                }
+                pnode = pnode->next;
+        }
+        plsfm->wpr_size = wpr_offset;
+        return 0;
+}
+
+/*Loads ACR bin to FB mem and bootstraps PMU with bootloader code
+ * start and end are addresses of ucode blob in non-WPR region*/
+static int gp106_bootstrap_hs_flcn(struct gk20a *g)
+{
+        struct mm_gk20a *mm = &g->mm;
+        struct vm_gk20a *vm = &mm->pmu.vm;
+        int err = 0;
+        u64 *acr_dmem;
+        u32 img_size_in_bytes = 0;
+        u32 status;
+        struct acr_desc *acr = &g->acr;
+        const struct firmware *acr_fw = acr->acr_fw;
+        struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1;
+        u32 *acr_ucode_header_t210_load;
+        u32 *acr_ucode_data_t210_load;
+        struct wpr_carveout_info wpr_inf;
+
+        gp106_dbg_pmu("");
+
+        if (!acr_fw) {
+                /*First time init case*/
+                acr_fw = nvgpu_request_firmware(g,
+                                GM20B_HSBIN_PMU_UCODE_IMAGE,
+                                NVGPU_REQUEST_FIRMWARE_NO_SOC);
+                if (!acr_fw) {
+                        gk20a_err(dev_from_gk20a(g), "pmu ucode get fail");
+                        return -ENOENT;
+                }
+                acr->acr_fw = acr_fw;
+                acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data;
+                acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data +
+                                acr->hsbin_hdr->header_offset);
+                acr_ucode_data_t210_load = (u32 *)(acr_fw->data +
+                                acr->hsbin_hdr->data_offset);
+                acr_ucode_header_t210_load = (u32 *)(acr_fw->data +
+                                acr->fw_hdr->hdr_offset);
+                img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256);
+
+                /* Lets patch the signatures first.. */
+                if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load,
+                                        (u32 *)(acr_fw->data +
+                                                acr->fw_hdr->sig_prod_offset),
+                                        (u32 *)(acr_fw->data +
+                                                acr->fw_hdr->sig_dbg_offset),
+                                        (u32 *)(acr_fw->data +
+                                                acr->fw_hdr->patch_loc),
+                                        (u32 *)(acr_fw->data +
+                                                acr->fw_hdr->patch_sig)) < 0) {
+                        gk20a_err(dev_from_gk20a(g), "patch signatures fail");
+                        err = -1;
+                        goto err_release_acr_fw;
+                }
+                err = gk20a_gmmu_alloc_map_sys(vm, img_size_in_bytes,
+                                &acr->acr_ucode);
+                if (err) {
+                        err = -ENOMEM;
+                        goto err_release_acr_fw;
+                }
+
+                g->ops.pmu.get_wpr(g, &wpr_inf);
+
+                acr_dmem = (u64 *)
+                        &(((u8 *)acr_ucode_data_t210_load)[
+                                        acr_ucode_header_t210_load[2]]);
+                acr->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)((u8 *)(
+                        acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]);
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_start =
+                                wpr_inf.nonwpr_base;
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_size =
+                                wpr_inf.size;
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.no_regions = 1;
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_offset = 0;
+
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_region_id = 1;
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
+                                                                                        0].region_id = 1;
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
+                        0].start_addr = (wpr_inf.wpr_base ) >> 8;
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
+                        0].end_addr = ((wpr_inf.wpr_base) + wpr_inf.size) >> 8;
+                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
+                        0].shadowmMem_startaddress = wpr_inf.nonwpr_base >> 8;
+
+                gk20a_mem_wr_n(g, &acr->acr_ucode, 0,
+                                acr_ucode_data_t210_load, img_size_in_bytes);
+
+                /*
+                 * In order to execute this binary, we will be using
+                 * a bootloader which will load this image into PMU IMEM/DMEM.
+                 * Fill up the bootloader descriptor for PMU HAL to use..
+                 * TODO: Use standard descriptor which the generic bootloader is
+                 * checked in.
+                 */
+
+                bl_dmem_desc->signature[0] = 0;
+                bl_dmem_desc->signature[1] = 0;
+                bl_dmem_desc->signature[2] = 0;
+                bl_dmem_desc->signature[3] = 0;
+                bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
+                flcn64_set_dma( &bl_dmem_desc->code_dma_base,
+                                                acr->acr_ucode.gpu_va);
+                bl_dmem_desc->non_sec_code_off  = acr_ucode_header_t210_load[0];
+                bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1];
+                bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5];
+                bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6];
+                bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */
+                flcn64_set_dma( &bl_dmem_desc->data_dma_base,
+                                        acr->acr_ucode.gpu_va +
+                                        (acr_ucode_header_t210_load[2]));
+                bl_dmem_desc->data_size = acr_ucode_header_t210_load[3];
+        } else
+                acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0;
+
+        status = pmu_exec_gen_bl(g, bl_dmem_desc, 1);
+        if (status != 0) {
+                err = status;
+                goto err_free_ucode_map;
+        }
+
+        /* sec2 reset - to keep it idle */
+        gk20a_writel(g, psec_falcon_engine_r(),
+                pwr_falcon_engine_reset_true_f());
+        udelay(10);
+        gk20a_writel(g, psec_falcon_engine_r(),
+                pwr_falcon_engine_reset_false_f());
+
+        return 0;
+err_free_ucode_map:
+        gk20a_gmmu_unmap_free(vm, &acr->acr_ucode);
+err_release_acr_fw:
+        release_firmware(acr_fw);
+        acr->acr_fw = NULL;
+        return err;
+}
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h
new file mode 100644
index 00000000..cd555eb8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __ACR_GP106_H_
+#define __ACR_GP106_H_
+
+#include "gm20b/acr_gm20b.h"
+#include "gm206/acr_gm206.h"
+
+#define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin"
+#define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin"
+#define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin"
+#define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin"
+
+struct lsf_ucode_desc_v1 {
+        u8  prd_keys[2][16];
+        u8  dbg_keys[2][16];
+        u32 b_prd_present;
+        u32 b_dbg_present;
+        u32 falcon_id;
+        u32 bsupports_versioning;
+        u32 version;
+        u32 dep_map_count;
+        u8  dep_map[LSF_FALCON_ID_END * 2 * 4];
+        u8  kdf[16];
+};
+
+struct lsf_wpr_header_v1 {
+        u32  falcon_id;
+        u32  lsb_offset;
+        u32  bootstrap_owner;
+        u32  lazy_bootstrap;
+        u32  bin_version;
+        u32  status;
+};
+
+struct lsf_lsb_header_v1 {
+        struct lsf_ucode_desc_v1 signature;
+        u32 ucode_off;
+        u32 ucode_size;
+        u32 data_size;
+        u32 bl_code_size;
+        u32 bl_imem_off;
+        u32 bl_data_off;
+        u32 bl_data_size;
+        u32 app_code_off;
+        u32 app_code_size;
+        u32 app_data_off;
+        u32 app_data_size;
+        u32 flags;
+};
+
+struct flcn_ucode_img_v1 {
+        u32 *header; /*only some falcons have header*/
+        u32 *data;
+        struct pmu_ucode_desc_v1 *desc;  /*only some falcons have descriptor*/
+        u32 data_size;
+        void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/
+        u8 load_entire_os_data; /* load the whole osData section at boot time.*/
+        struct lsf_ucode_desc_v1 *lsf_desc; /* NULL if not a light secure falcon.*/
+        u8 free_res_allocs;/*True if there a resources to freed by the client.*/
+        u32 flcn_inst;
+};
+
+struct lsfm_managed_ucode_img_v2 {
+        struct lsfm_managed_ucode_img_v2 *next;
+        struct lsf_wpr_header_v1 wpr_header;
+        struct lsf_lsb_header_v1 lsb_header;
+        union flcn_bl_generic_desc_v1 bl_gen_desc;
+        u32 bl_gen_desc_size;
+        u32 full_ucode_size;
+        struct flcn_ucode_img_v1 ucode_img;
+};
+struct ls_flcn_mgr_v1 {
+        u16 managed_flcn_cnt;
+        u32 wpr_size;
+        u32 disable_mask;
+        struct lsfm_managed_ucode_img_v2 *ucode_img_list;
+        void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
+};
+
+struct flcn_acr_region_prop_v1 {
+        u32   start_addr;
+        u32   end_addr;
+        u32   region_id;
+        u32   read_mask;
+        u32   write_mask;
+        u32   client_mask;
+        u32   shadowmMem_startaddress;
+};
+
+/*!
+ * no_regions   - Number of regions used.
+ * region_props   - Region properties
+ */
+struct flcn_acr_regions_v1 {
+        u32                     no_regions;
+        struct flcn_acr_region_prop_v1   region_props[T210_FLCN_ACR_MAX_REGIONS];
+};
+
+struct flcn_acr_desc_v1 {
+        union {
+                u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
+        } ucode_reserved_space;
+        u32 signatures[4];
+        /*Always 1st*/
+        u32 wpr_region_id;
+        u32 wpr_offset;
+        u32 mmu_mem_range;
+        struct flcn_acr_regions_v1 regions;
+        u32 nonwpr_ucode_blob_size;
+        u64 nonwpr_ucode_blob_start;
+        u32 dummy[4];  //ACR_BSI_VPR_DESC
+};
+
+void gp106_init_secure_pmu(struct gpu_ops *gops);
+
+#endif /*__PMU_GP106_H_*/
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c
new file mode 100644
index 00000000..8be4314d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/bios_gp106.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gm206/bios_gm206.h"
+#include "bios_gp106.h"
+#include "hw_gc6_gp106.h"
+
+static void gp106_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
+        u32 reg, u32 stride, u32 count, u32 data_table_offset)
+{
+        u8 i;
+        u32 data, strap, index;
+
+        if (*condition) {
+
+                strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
+
+                index = g->bios.mem_strap_xlat_tbl_ptr ?
+                        gm206_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
+                                strap) : strap;
+
+                for (i = 0; i < count; i++) {
+                        data = gm206_bios_read_u32(g, data_table_offset + ((i *
+                                g->bios.mem_strap_data_count + index) *
+                                sizeof(u32)));
+                        gk20a_writel(g, reg, data);
+                        reg += stride;
+                }
+        }
+}
+
+static void gp106_init_condition(struct gk20a *g, bool *condition,
+        u32 condition_id)
+{
+        struct condition_entry entry;
+
+        entry.cond_addr = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
+                sizeof(entry)*condition_id);
+        entry.cond_mask = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
+                sizeof(entry)*condition_id + 4);
+        entry.cond_compare = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
+                sizeof(entry)*condition_id + 8);
+
+        if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
+                != entry.cond_compare) {
+                *condition = false;
+        }
+}
+
+static int gp106_execute_script(struct gk20a *g, u32 offset)
+{
+        u8 opcode;
+        u32 ip;
+        u32 operand[8];
+        bool condition, end;
+        int status = 0;
+
+        ip = offset;
+        condition = true;
+        end = false;
+
+        while (!end) {
+
+                opcode = gm206_bios_read_u8(g, ip++);
+
+                switch (opcode) {
+
+                case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
+                        operand[0] = gm206_bios_read_u32(g, ip);
+                        operand[1] = gm206_bios_read_u8(g, ip+4);
+                        operand[2] = gm206_bios_read_u8(g, ip+5);
+                        ip += 6;
+
+                        gp106_init_xmemsel_zm_nv_reg_array(g, &condition,
+                                operand[0], operand[1], operand[2], ip);
+                        ip += operand[2] * sizeof(u32) *
+                                g->bios.mem_strap_data_count;
+                        break;
+
+                case INIT_CONDITION:
+                        operand[0] = gm206_bios_read_u8(g, ip);
+                        ip++;
+
+                        gp106_init_condition(g, &condition, operand[0]);
+                        break;
+
+                case INIT_RESUME:
+                        condition = true;
+                        break;
+
+                case INIT_DONE:
+                        end = true;
+                        break;
+
+                default:
+                        gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
+                        end = true;
+                        status = -EINVAL;
+                        break;
+                }
+        }
+
+        return status;
+}
+
+void gp106_init_bios(struct gpu_ops *gops)
+{
+        gm206_init_bios(gops);
+        gops->bios.execute_script = gp106_execute_script;
+}
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.h b/drivers/gpu/nvgpu/gp106/bios_gp106.h
new file mode 100644
index 00000000..f47d11ca
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/bios_gp106.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_BIOS_GP106_H
+#define NVGPU_BIOS_GP106_H
+
+struct gpu_ops;
+
+#define INIT_DONE 0x71
+#define INIT_RESUME 0x72
+#define INIT_CONDITION 0x75
+#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
+
+struct condition_entry {
+        u32 cond_addr;
+        u32 cond_mask;
+        u32 cond_compare;
+} __packed;
+
+void gp106_init_bios(struct gpu_ops *gops);
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
new file mode 100644
index 00000000..b4d1afbc
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+
+#include "clk/clk_arb.h"
+#include "clk_arb_gp106.h"
+
+static u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
+{
+        (void)g;
+        return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK);
+}
+
+static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+                u16 *min_mhz, u16 *max_mhz)
+{
+        enum nv_pmu_clk_clkwhich clkwhich;
+        struct clk_set_info *p0_info;
+        struct clk_set_info *p5_info;
+        struct avfsfllobjs *pfllobjs =  &(g->clk_pmu.avfs_fllobjs);
+
+        u16 limit_min_mhz;
+
+        switch (api_domain) {
+        case CTRL_CLK_DOMAIN_MCLK:
+                clkwhich = clkwhich_mclk;
+                break;
+
+        case CTRL_CLK_DOMAIN_GPC2CLK:
+                clkwhich = clkwhich_gpc2clk;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        p5_info = pstate_get_clk_set_info(g,
+                        CTRL_PERF_PSTATE_P5, clkwhich);
+        if (!p5_info)
+                return -EINVAL;
+
+        p0_info = pstate_get_clk_set_info(g,
+                        CTRL_PERF_PSTATE_P0, clkwhich);
+        if (!p0_info)
+                return -EINVAL;
+
+        limit_min_mhz = p5_info->min_mhz;
+        /* WAR for DVCO min */
+        if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK)
+                if ((pfllobjs->max_min_freq_mhz) &&
+                (pfllobjs->max_min_freq_mhz > limit_min_mhz))
+                        limit_min_mhz = pfllobjs->max_min_freq_mhz;
+
+        *min_mhz = limit_min_mhz;
+        *max_mhz = p0_info->max_mhz;
+
+        return 0;
+}
+
+static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
+                u16 *default_mhz)
+{
+        enum nv_pmu_clk_clkwhich clkwhich;
+        struct clk_set_info *p0_info;
+
+        switch (api_domain) {
+        case CTRL_CLK_DOMAIN_MCLK:
+                clkwhich = clkwhich_mclk;
+                break;
+
+        case CTRL_CLK_DOMAIN_GPC2CLK:
+                clkwhich = clkwhich_gpc2clk;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        p0_info = pstate_get_clk_set_info(g,
+                        CTRL_PERF_PSTATE_P0, clkwhich);
+        if (!p0_info)
+                return -EINVAL;
+
+        *default_mhz = p0_info->max_mhz;
+
+        return 0;
+}
+
+void gp106_init_clk_arb_ops(struct gpu_ops *gops)
+{
+        gops->clk_arb.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains;
+        gops->clk_arb.get_arbiter_clk_range = gp106_get_arbiter_clk_range;
+        gops->clk_arb.get_arbiter_clk_default = gp106_get_arbiter_clk_default;
+}
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h
new file mode 100644
index 00000000..a9877199
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef CLK_ARB_GP106_H
+#define CLK_ARB_GP106_H
+
+void gp106_init_clk_arb_ops(struct gpu_ops *gops);
+
+#endif /* CLK_ARB_GP106_H */
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
new file mode 100644
index 00000000..4c9bc782
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -0,0 +1,273 @@
+/*
+ * GP106 Clocks
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>        /* for mdelay */
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/clk/tegra.h>
+#include <linux/tegra-fuse.h>
+
+#include "gk20a/gk20a.h"
+#include "hw_trim_gp106.h"
+#include "clk_gp106.h"
+#include "clk/clk_arb.h"
+
+#define gk20a_dbg_clk(fmt, arg...) \
+        gk20a_dbg(gpu_dbg_clk, fmt, ##arg)
+
+#ifdef CONFIG_DEBUG_FS
+static int clk_gp106_debugfs_init(struct gk20a *g);
+#endif
+
+#define NUM_NAMEMAPS    4
+#define XTAL4X_KHZ 108000
+
+
+static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *);
+static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain);
+static u32 gp106_crystal_clk_hz(struct gk20a *g)
+{
+        return (XTAL4X_KHZ * 1000);
+}
+
+static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain)
+{
+        struct clk_gk20a *clk = &g->clk;
+        u32 freq_khz;
+        u32 i;
+        struct namemap_cfg *c = NULL;
+
+        for (i = 0; i < clk->namemap_num; i++) {
+                if (api_domain == clk->namemap_xlat_table[i]) {
+                        c = &clk->clk_namemap[i];
+                        break;
+                }
+        }
+
+        if (!c)
+                return 0;
+
+        freq_khz = c->is_counter ? c->scale * gp106_get_rate_cntr(g, c) :
+                0; /* TODO: PLL read */
+
+        /* Convert to MHZ */
+        return (u16) (freq_khz/1000);
+}
+
+static int gp106_init_clk_support(struct gk20a *g) {
+        struct clk_gk20a *clk = &g->clk;
+        u32 err = 0;
+
+        gk20a_dbg_fn("");
+
+        mutex_init(&clk->clk_mutex);
+
+        clk->clk_namemap = (struct namemap_cfg *)
+                kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL);
+
+        if (!clk->clk_namemap)
+                return -ENOMEM;
+
+        clk->namemap_xlat_table = kcalloc(NUM_NAMEMAPS, sizeof(u32),
+                GFP_KERNEL);
+
+        if (!clk->namemap_xlat_table) {
+                kfree(clk->clk_namemap);
+                return -ENOMEM;
+        }
+
+        clk->clk_namemap[0] = (struct namemap_cfg) {
+                .namemap = CLK_NAMEMAP_INDEX_GPC2CLK,
+                .is_enable = 1,
+                .is_counter = 1,
+                .g = g,
+                .cntr.reg_ctrl_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(),
+                .cntr.reg_ctrl_idx  =
+                        trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(),
+                .cntr.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(),
+                .name = "gpc2clk",
+                .scale = 1
+        };
+        clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPC2CLK;
+        clk->clk_namemap[1] = (struct namemap_cfg) {
+                .namemap = CLK_NAMEMAP_INDEX_SYS2CLK,
+                .is_enable = 1,
+                .is_counter = 1,
+                .g = g,
+                .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(),
+                .cntr.reg_ctrl_idx  = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(),
+                .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r(),
+                .name = "sys2clk",
+                .scale = 1
+        };
+        clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYS2CLK;
+        clk->clk_namemap[2] = (struct namemap_cfg) {
+                .namemap = CLK_NAMEMAP_INDEX_XBAR2CLK,
+                .is_enable = 1,
+                .is_counter = 1,
+                .g = g,
+                .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(),
+                .cntr.reg_ctrl_idx  = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(),
+                .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r(),
+                .name = "xbar2clk",
+                .scale = 1
+        };
+        clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBAR2CLK;
+        clk->clk_namemap[3] = (struct namemap_cfg) {
+                .namemap = CLK_NAMEMAP_INDEX_DRAMCLK,
+                .is_enable = 1,
+                .is_counter = 1,
+                .g = g,
+                .cntr.reg_ctrl_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(),
+                .cntr.reg_ctrl_idx  =
+                        trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(),
+                .cntr.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(),
+                .name = "dramdiv2_rec_clk1",
+                .scale = 2
+        };
+        clk->namemap_xlat_table[3] = CTRL_CLK_DOMAIN_MCLK;
+
+        clk->namemap_num = NUM_NAMEMAPS;
+
+        clk->g = g;
+
+#ifdef CONFIG_DEBUG_FS
+        if (!clk->debugfs_set) {
+                if (!clk_gp106_debugfs_init(g))
+                        clk->debugfs_set = true;
+        }
+#endif
+        return err;
+}
+
+static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
+        u32 save_reg;
+        u32 retries;
+        u32 cntr = 0;
+
+        struct clk_gk20a *clk = &g->clk;
+
+        if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr)
+                return 0;
+
+        mutex_lock(&clk->clk_mutex);
+
+        /* Save the register */
+        save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr);
+
+        /* Disable and reset the current clock */
+        gk20a_writel(g, c->cntr.reg_ctrl_addr,
+                                 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() |
+                                 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
+
+        /* Force wb() */
+        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+
+        /* Wait for reset to happen */
+        retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES;
+        do {
+                udelay(CLK_DEFAULT_CNTRL_SETTLE_USECS);
+        } while ((--retries) && (cntr = gk20a_readl(g, c->cntr.reg_cntr_addr)));
+
+        if (!retries) {
+                gk20a_err(dev_from_gk20a(g),
+             "unable to settle counter reset, bailing");
+                goto read_err;
+        }
+        /* Program counter */
+        gk20a_writel(g, c->cntr.reg_ctrl_addr,
+                                        trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f()          |
+                                        trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f()           |
+                                        trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f()         |
+                                        trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f()         |
+                                        trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f()         |
+                                        trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS)  |
+                                        c->cntr.reg_ctrl_idx);
+        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+
+        udelay(XTAL_CNTR_DELAY);
+
+        cntr = XTAL_SCALE_TO_KHZ * gk20a_readl(g, c->cntr.reg_cntr_addr);
+
+read_err:
+        /* reset and restore control register */
+        gk20a_writel(g, c->cntr.reg_ctrl_addr,
+                                 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() |
+                                 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
+        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+        gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg);
+        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+        mutex_unlock(&clk->clk_mutex);
+
+        return cntr;
+
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int gp106_get_rate_show(void *data , u64 *val) {
+        struct namemap_cfg *c = (struct namemap_cfg *) data;
+        struct gk20a *g = c->g;
+
+        *val = c->is_counter ? gp106_get_rate_cntr(g, c) : 0 /* TODO PLL read */;
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n");
+
+
+static int clk_gp106_debugfs_init(struct gk20a *g) {
+        struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+
+        struct dentry *gpu_root = platform->debugfs;
+        struct dentry *clocks_root;
+        struct dentry *d;
+        unsigned int i;
+
+        if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
+                return -ENOMEM;
+
+        gk20a_dbg(gpu_dbg_info, "g=%p", g);
+
+        for (i = 0; i < g->clk.namemap_num; i++) {
+                if (g->clk.clk_namemap[i].is_enable) {
+                        d = debugfs_create_file(
+                                g->clk.clk_namemap[i].name,
+                                S_IRUGO,
+                                clocks_root,
+                                &g->clk.clk_namemap[i],
+                                &get_rate_fops);
+                        if (!d)
+                                goto err_out;
+                }
+        }
+        return 0;
+
+err_out:
+        pr_err("%s: Failed to make debugfs node\n", __func__);
+        debugfs_remove_recursive(clocks_root);
+        return -ENOMEM;
+}
+#endif /* CONFIG_DEBUG_FS */
+
+void gp106_init_clk_ops(struct gpu_ops *gops) {
+        gops->clk.init_clk_support = gp106_init_clk_support;
+        gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz;
+        gops->clk.get_rate = gp106_clk_get_rate;
+}
+
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h
new file mode 100644
index 00000000..7df4b974
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef CLK_GP106_H
+#define CLK_GP106_H
+
+#include <linux/mutex.h>
+
+#define CLK_NAMEMAP_INDEX_GPC2CLK       0x00
+#define CLK_NAMEMAP_INDEX_XBAR2CLK      0x02
+#define CLK_NAMEMAP_INDEX_SYS2CLK       0x07    /* SYSPLL */
+#define CLK_NAMEMAP_INDEX_DRAMCLK       0x20    /* DRAMPLL */
+
+#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
+#define CLK_DEFAULT_CNTRL_SETTLE_USECS   5
+
+#define XTAL_CNTR_CLKS          27000   /* 1000usec at 27KHz XTAL */
+#define XTAL_CNTR_DELAY         1000    /* we need acuracy up to the ms   */
+#define XTAL_SCALE_TO_KHZ       1
+
+
+
+struct namemap_cfg {
+        u32 namemap;
+        u32 is_enable;  /* Namemap enabled */
+        u32 is_counter; /* Using cntr */
+        struct gk20a *g;
+        union {
+                struct {
+                        u32 reg_ctrl_addr;
+                        u32 reg_ctrl_idx;
+                        u32 reg_cntr_addr;
+                } cntr;
+                struct {
+                        /* Todo */
+                } pll;
+        };
+        u32 scale;
+        char name[24];
+};
+
+void gp106_init_clk_ops(struct gpu_ops *gops);
+
+#endif /* CLK_GP106_H */
diff --git a/drivers/gpu/nvgpu/gp106/fb_gp106.c b/drivers/gpu/nvgpu/gp106/fb_gp106.c
new file mode 100644
index 00000000..ef9f1094
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/fb_gp106.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "gk20a/gk20a.h"
+#include "gp10b/fb_gp10b.h"
+#include "hw_fb_gp106.h"
+
+#define HW_SCRUB_TIMEOUT_DEFAULT        100 /* usec */
+#define HW_SCRUB_TIMEOUT_MAX            2000000 /* usec */
+
+static void gp106_fb_reset(struct gk20a *g)
+{
+        int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT;
+        /* wait for memory to be accessible */
+        do {
+                u32 w = gk20a_readl(g, fb_niso_scrub_status_r());
+                if (fb_niso_scrub_status_flag_v(w)) {
+                        gk20a_dbg_fn("done");
+                        break;
+                }
+                udelay(HW_SCRUB_TIMEOUT_DEFAULT);
+        } while (--retries);
+}
+
+void gp106_init_fb(struct gpu_ops *gops)
+{
+        gp10b_init_fb(gops);
+
+        gops->fb.init_fs_state = NULL;
+        gops->fb.reset = gp106_fb_reset;
+}
diff --git a/drivers/gpu/nvgpu/gp106/fb_gp106.h b/drivers/gpu/nvgpu/gp106/fb_gp106.h
new file mode 100644
index 00000000..87b371e1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/fb_gp106.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef FB_GP106_H
+#define FB_GP106_H
+struct gpu_ops;
+
+void gp106_init_fb(struct gpu_ops *gops);
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.c b/drivers/gpu/nvgpu/gp106/fifo_gp106.c
new file mode 100644
index 00000000..3c70d517
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gp10b/fifo_gp10b.h"
+#include "fifo_gp106.h"
+#include "hw_ccsr_gp106.h"
+#include "hw_fifo_gp106.h"
+
+static u32 gp106_fifo_get_num_fifos(struct gk20a *g)
+{
+        return ccsr_channel__size_1_v();
+}
+
+void gp106_init_fifo(struct gpu_ops *gops)
+{
+        gp10b_init_fifo(gops);
+        gops->fifo.get_num_fifos = gp106_fifo_get_num_fifos;
+        gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
+}
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.h b/drivers/gpu/nvgpu/gp106/fifo_gp106.h
new file mode 100644
index 00000000..1bcec9ef
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_FIFO_GP106_H
+#define NVGPU_FIFO_GP106_H
+struct gpu_ops;
+void gp106_init_fifo(struct gpu_ops *gops);
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c
new file mode 100644
index 00000000..29870d60
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c
@@ -0,0 +1,649 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef __gp106_gating_reglist_h__
+#define __gp106_gating_reglist_h__
+
+#include <linux/types.h>
+#include "gp106_gating_reglist.h"
+
+struct gating_desc {
+        u32 addr;
+        u32 prod;
+        u32 disable;
+};
+/* slcg bus */
+static const struct gating_desc gp106_slcg_bus[] = {
+        {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
+};
+
+/* slcg ce2 */
+static const struct gating_desc gp106_slcg_ce2[] = {
+        {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
+};
+
+/* slcg chiplet */
+static const struct gating_desc gp106_slcg_chiplet[] = {
+        {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c1fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c2fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d1fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d2fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
+};
+
+/* slcg fb */
+static const struct gating_desc gp106_slcg_fb[] = {
+        {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
+};
+
+/* slcg fifo */
+static const struct gating_desc gp106_slcg_fifo[] = {
+        {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe},
+};
+
+/* slcg gr */
+static const struct gating_desc gp106_slcg_gr[] = {
+        {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe},
+        {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
+        {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
+        {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
+        {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
+        {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
+        {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
+        {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
+        {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
+        {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe},
+        {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
+        {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},
+        {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe},
+        {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
+        {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
+        {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
+        {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
+        {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
+        {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
+        {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
+        {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
+        {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
+        {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
+        {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
+        {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
+        {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
+        {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
+        {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
+        {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
+        {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
+        {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
+        {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x0000ffff},
+        {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x0000ffff},
+        {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
+};
+
+/* slcg ltc */
+static const struct gating_desc gp106_slcg_ltc[] = {
+        {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
+};
+
+/* slcg perf */
+static const struct gating_desc gp106_slcg_perf[] = {
+        {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc418, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc618, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc818, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bca18, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8418, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8618, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8818, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8a18, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
+};
+
+/* slcg PriRing */
+static const struct gating_desc gp106_slcg_priring[] = {
+        {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
+};
+
+/* slcg pmu */
+static const struct gating_desc gp106_slcg_pmu[] = {
+        {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
+        {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
+        {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* therm gr */
+static const struct gating_desc gp106_slcg_therm[] = {
+        {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* slcg Xbar */
+static const struct gating_desc gp106_slcg_xbar[] = {
+        {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe},
+        {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe},
+        {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe},
+};
+
+/* blcg bus */
+static const struct gating_desc gp106_blcg_bus[] = {
+        {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* blcg ce */
+static const struct gating_desc gp106_blcg_ce[] = {
+        {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg fb */
+static const struct gating_desc gp106_blcg_fb[] = {
+        {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
+        {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
+};
+
+/* blcg fifo */
+static const struct gating_desc gp106_blcg_fifo[] = {
+        {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg gr */
+static const struct gating_desc gp106_blcg_gr[] = {
+        {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
+        {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
+        {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
+        {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
+        {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
+        {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
+        {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
+        {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
+        {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
+        {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
+        {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
+        {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
+        {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
+        {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
+        {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
+        {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
+        {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
+        {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
+        {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg ltc */
+static const struct gating_desc gp106_blcg_ltc[] = {
+        {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
+};
+
+/* blcg pmu */
+static const struct gating_desc gp106_blcg_pmu[] = {
+        {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
+};
+
+/* blcg Xbar */
+static const struct gating_desc gp106_blcg_xbar[] = {
+        {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000},
+        {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000},
+        {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000},
+        {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* pg gr */
+static const struct gating_desc gp106_pg_gr[] = {
+};
+
+/* inline functions */
+void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_bus[i].addr,
+                                gp106_slcg_bus[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_bus[i].addr,
+                                 gp106_slcg_bus[i].disable);
+        }
+}
+
+void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_ce2[i].addr,
+                                gp106_slcg_ce2[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_ce2[i].addr,
+                                 gp106_slcg_ce2[i].disable);
+        }
+}
+
+void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_chiplet[i].addr,
+                                gp106_slcg_chiplet[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_chiplet[i].addr,
+                                 gp106_slcg_chiplet[i].disable);
+        }
+}
+
+void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+}
+
+void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_fb[i].addr,
+                                gp106_slcg_fb[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_fb[i].addr,
+                                 gp106_slcg_fb[i].disable);
+        }
+}
+
+void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_fifo[i].addr,
+                                gp106_slcg_fifo[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_fifo[i].addr,
+                                 gp106_slcg_fifo[i].disable);
+        }
+}
+
+void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_gr[i].addr,
+                                gp106_slcg_gr[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_gr[i].addr,
+                                 gp106_slcg_gr[i].disable);
+        }
+}
+
+void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_ltc[i].addr,
+                                gp106_slcg_ltc[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_ltc[i].addr,
+                                gp106_slcg_ltc[i].disable);
+        }
+}
+
+void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_perf[i].addr,
+                                gp106_slcg_perf[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_perf[i].addr,
+                                gp106_slcg_perf[i].disable);
+        }
+}
+
+void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_priring[i].addr,
+                                gp106_slcg_priring[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_priring[i].addr,
+                                gp106_slcg_priring[i].disable);
+        }
+}
+
+void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_pmu[i].addr,
+                                gp106_slcg_pmu[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_pmu[i].addr,
+                                gp106_slcg_pmu[i].disable);
+        }
+}
+
+void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_therm[i].addr,
+                                gp106_slcg_therm[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_therm[i].addr,
+                                gp106_slcg_therm[i].disable);
+        }
+}
+
+void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_xbar[i].addr,
+                                gp106_slcg_xbar[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_xbar[i].addr,
+                                gp106_slcg_xbar[i].disable);
+        }
+}
+
+void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_bus[i].addr,
+                                gp106_blcg_bus[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_bus[i].addr,
+                                gp106_blcg_bus[i].disable);
+        }
+}
+
+void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_ce[i].addr,
+                                gp106_blcg_ce[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_ce[i].addr,
+                                gp106_blcg_ce[i].disable);
+        }
+}
+
+void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_fb[i].addr,
+                                gp106_blcg_fb[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_fb[i].addr,
+                                gp106_blcg_fb[i].disable);
+        }
+}
+
+void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_fifo[i].addr,
+                                gp106_blcg_fifo[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_fifo[i].addr,
+                                gp106_blcg_fifo[i].disable);
+        }
+}
+
+void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_gr[i].addr,
+                                gp106_blcg_gr[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_gr[i].addr,
+                                gp106_blcg_gr[i].disable);
+        }
+}
+
+void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_ltc[i].addr,
+                                gp106_blcg_ltc[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_ltc[i].addr,
+                                gp106_blcg_ltc[i].disable);
+        }
+}
+
+void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_pmu[i].addr,
+                                gp106_blcg_pmu[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_pmu[i].addr,
+                                gp106_blcg_pmu[i].disable);
+        }
+}
+
+void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_xbar[i].addr,
+                                gp106_blcg_xbar[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_xbar[i].addr,
+                                gp106_blcg_xbar[i].disable);
+        }
+}
+
+void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_pg_gr[i].addr,
+                                gp106_pg_gr[i].prod);
+                else
+                        gk20a_writel(g, gp106_pg_gr[i].addr,
+                                gp106_pg_gr[i].disable);
+        }
+}
+
+#endif /* __gp106_gating_reglist_h__ */
diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h
new file mode 100644
index 00000000..423ccf54
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "gk20a/gk20a.h"
+
+void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
+        bool prod);
+
+void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
+        bool prod);
+
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c
new file mode 100644
index 00000000..1f47cc5a
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c
@@ -0,0 +1,50 @@
+/*
+ * GP106 Graphics Context
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gr_ctx_gp106.h"
+#include "nvgpu_gpuid_t18x.h"
+
+static int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name)
+{
+        u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
+
+        switch (ver) {
+                case NVGPU_GPUID_GP104:
+                        sprintf(name, "%s/%s", "gp104",
+                                        GP104_NETLIST_IMAGE_FW_NAME);
+                        break;
+                case NVGPU_GPUID_GP106:
+                        sprintf(name, "%s/%s", "gp106",
+                                        GP106_NETLIST_IMAGE_FW_NAME);
+                        break;
+                default:
+                        gk20a_err(g->dev, "no support for GPUID %x", ver);
+        }
+
+        return 0;
+}
+
+static bool gr_gp106_is_firmware_defined(void)
+{
+        return true;
+}
+
+void gp106_init_gr_ctx(struct gpu_ops *gops)
+{
+        gops->gr_ctx.get_netlist_name = gr_gp106_get_netlist_name;
+        gops->gr_ctx.is_fw_defined = gr_gp106_is_firmware_defined;
+        gops->gr_ctx.use_dma_for_fw_bootstrap = false;
+}
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h
new file mode 100644
index 00000000..fef80abb
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __GR_CTX_GP106_H__
+#define __GR_CTX_GP106_H__
+
+#include "gk20a/gr_ctx_gk20a.h"
+
+/* production netlist, one and only one from below */
+#define GP106_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_C
+#define GP104_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D
+
+void gp106_init_gr_ctx(struct gpu_ops *gops);
+
+#endif /*__GR_CTX_GP106_H__*/
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
new file mode 100644
index 00000000..8d8376d3
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -0,0 +1,239 @@
+/*
+ * GP106 GPU GR
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
+
+#include "gk20a/gr_gk20a.h"
+
+#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
+#include "gp10b/gr_gp10b.h"
+#include "gr_gp106.h"
+#include "hw_gr_gp106.h"
+
+static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num)
+{
+        bool valid = false;
+
+        switch (class_num) {
+        case PASCAL_COMPUTE_A:
+        case PASCAL_COMPUTE_B:
+        case PASCAL_A:
+        case PASCAL_B:
+        case PASCAL_DMA_COPY_A:
+        case PASCAL_DMA_COPY_B:
+                valid = true;
+                break;
+
+        case MAXWELL_COMPUTE_B:
+        case MAXWELL_B:
+        case FERMI_TWOD_A:
+        case KEPLER_DMA_COPY_A:
+        case MAXWELL_DMA_COPY_A:
+                valid = true;
+                break;
+
+        default:
+                break;
+        }
+        gk20a_dbg_info("class=0x%x valid=%d", class_num, valid);
+        return valid;
+}
+
+static u32 gr_gp106_pagepool_default_size(struct gk20a *g)
+{
+        return gr_scc_pagepool_total_pages_hwmax_value_v();
+}
+
+static void gr_gp106_set_go_idle_timeout(struct gk20a *g, u32 data)
+{
+        gk20a_writel(g, gr_fe_go_idle_timeout_r(), data);
+}
+
+static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
+                                     u32 class_num, u32 offset, u32 data)
+{
+        gk20a_dbg_fn("");
+
+        if (class_num == PASCAL_COMPUTE_B) {
+                switch (offset << 2) {
+                case NVC0C0_SET_SHADER_EXCEPTIONS:
+                        gk20a_gr_set_shader_exceptions(g, data);
+                        break;
+                default:
+                        goto fail;
+                }
+        }
+
+        if (class_num == PASCAL_B) {
+                switch (offset << 2) {
+                case NVC097_SET_SHADER_EXCEPTIONS:
+                        gk20a_gr_set_shader_exceptions(g, data);
+                        break;
+                case NVC097_SET_CIRCULAR_BUFFER_SIZE:
+                        g->ops.gr.set_circular_buffer_size(g, data);
+                        break;
+                case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
+                        g->ops.gr.set_alpha_circular_buffer_size(g, data);
+                        break;
+                case NVC097_SET_GO_IDLE_TIMEOUT:
+                        gr_gp106_set_go_idle_timeout(g, data);
+                        break;
+                default:
+                        goto fail;
+                }
+        }
+        return 0;
+
+fail:
+        return -EINVAL;
+}
+
+static void gr_gp106_cb_size_default(struct gk20a *g)
+{
+        struct gr_gk20a *gr = &g->gr;
+
+        if (!gr->attrib_cb_default_size)
+                gr->attrib_cb_default_size = 0x800;
+        gr->alpha_cb_default_size =
+                gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
+}
+
+static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
+                                struct gr_ctx_desc *gr_ctx,
+                                struct vm_gk20a *vm, u32 class,
+                                u32 graphics_preempt_mode,
+                                u32 compute_preempt_mode)
+{
+        int err = 0;
+
+        if (class == PASCAL_B && g->gr.t18x.ctx_vars.force_preemption_gfxp)
+                graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
+
+        if (class == PASCAL_COMPUTE_B &&
+                        g->gr.t18x.ctx_vars.force_preemption_cilp)
+                compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
+
+        /* check for invalid combinations */
+        if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
+                return -EINVAL;
+
+        if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) &&
+                   (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP))
+                return -EINVAL;
+
+        /* set preemption modes */
+        switch (graphics_preempt_mode) {
+        case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP:
+                {
+                u32 spill_size =
+                        gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
+                        gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
+                u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
+                        gr_scc_pagepool_total_pages_byte_granularity_v();
+                u32 betacb_size = g->gr.attrib_cb_default_size +
+                                  (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
+                                   gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
+                u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
+                                  gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
+                                  g->gr.max_tpc_count;
+                attrib_cb_size = ALIGN(attrib_cb_size, 128);
+
+                gk20a_dbg_info("gfxp context spill_size=%d", spill_size);
+                gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size);
+                gk20a_dbg_info("gfxp context attrib_cb_size=%d",
+                                attrib_cb_size);
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        g->gr.t18x.ctx_vars.preempt_image_size,
+                                        &gr_ctx->t18x.preempt_ctxsw_buffer);
+                if (err) {
+                        gk20a_err(dev_from_gk20a(g),
+                                  "cannot allocate preempt buffer");
+                        goto fail;
+                }
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        spill_size,
+                                        &gr_ctx->t18x.spill_ctxsw_buffer);
+                if (err) {
+                        gk20a_err(dev_from_gk20a(g),
+                                  "cannot allocate spill buffer");
+                        goto fail_free_preempt;
+                }
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        attrib_cb_size,
+                                        &gr_ctx->t18x.betacb_ctxsw_buffer);
+                if (err) {
+                        gk20a_err(dev_from_gk20a(g),
+                                  "cannot allocate beta buffer");
+                        goto fail_free_spill;
+                }
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        pagepool_size,
+                                        &gr_ctx->t18x.pagepool_ctxsw_buffer);
+                if (err) {
+                        gk20a_err(dev_from_gk20a(g),
+                                  "cannot allocate page pool");
+                        goto fail_free_betacb;
+                }
+
+                gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
+                break;
+                }
+
+        case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI:
+                gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
+                break;
+
+        default:
+                break;
+        }
+
+        if (class == PASCAL_COMPUTE_B) {
+                switch (compute_preempt_mode) {
+                case NVGPU_COMPUTE_PREEMPTION_MODE_WFI:
+                case NVGPU_COMPUTE_PREEMPTION_MODE_CTA:
+                case NVGPU_COMPUTE_PREEMPTION_MODE_CILP:
+                        gr_ctx->compute_preempt_mode = compute_preempt_mode;
+                        break;
+                default:
+                        break;
+                }
+        }
+
+        return 0;
+
+fail_free_betacb:
+        gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
+fail_free_spill:
+        gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
+fail_free_preempt:
+        gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
+fail:
+        return err;
+}
+
+void gp106_init_gr(struct gpu_ops *gops)
+{
+        gp10b_init_gr(gops);
+        gops->gr.is_valid_class = gr_gp106_is_valid_class;
+        gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size;
+        gops->gr.handle_sw_method = gr_gp106_handle_sw_method;
+        gops->gr.cb_size_default = gr_gp106_cb_size_default;
+        gops->gr.init_preemption_state = NULL;
+        gops->gr.set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode;
+}
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h
new file mode 100644
index 00000000..4fe22ee9
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h
@@ -0,0 +1,26 @@
+/*
+ * GP106 GPU GR
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_GR_GP106_H_
+#define _NVGPU_GR_GP106_H_
+
+enum {
+        PASCAL_B                 = 0xC197,
+        PASCAL_COMPUTE_B         = 0xC1C0,
+};
+
+void gp106_init_gr(struct gpu_ops *gops);
+
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
new file mode 100644
index 00000000..ee361953
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -0,0 +1,259 @@
+/*
+ * GP106 HAL interface
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/printk.h>
+
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+
+#include "gp10b/gr_gp10b.h"
+#include "gp10b/mc_gp10b.h"
+#include "gp106/ltc_gp106.h"
+#include "gp10b/mm_gp10b.h"
+#include "gp10b/ce_gp10b.h"
+#include "gp106/fifo_gp106.h"
+#include "gp106/regops_gp106.h"
+#include "gp10b/cde_gp10b.h"
+#include "gp106/therm_gp106.h"
+#include "gp106/xve_gp106.h"
+
+#include "gp106/bios_gp106.h"
+
+#include "gm20b/gr_gm20b.h"
+#include "gm20b/fifo_gm20b.h"
+#include "gm20b/pmu_gm20b.h"
+#include "gp106/clk_gp106.h"
+#include "gp106/clk_arb_gp106.h"
+
+#include "gp106/mm_gp106.h"
+#include "gp106/pmu_gp106.h"
+#include "gp106/gr_ctx_gp106.h"
+#include "gp106/gr_gp106.h"
+#include "gp106/fb_gp106.h"
+#include "gp106/gp106_gating_reglist.h"
+#include "nvgpu_gpuid_t18x.h"
+#include "hw_proj_gp106.h"
+#include "gk20a/dbg_gpu_gk20a.h"
+#include "gk20a/css_gr_gk20a.h"
+
+static struct gpu_ops gp106_ops = {
+        .clock_gating = {
+                .slcg_bus_load_gating_prod =
+                        gp106_slcg_bus_load_gating_prod,
+                .slcg_ce2_load_gating_prod =
+                        gp106_slcg_ce2_load_gating_prod,
+                .slcg_chiplet_load_gating_prod =
+                        gp106_slcg_chiplet_load_gating_prod,
+                .slcg_ctxsw_firmware_load_gating_prod =
+                        gp106_slcg_ctxsw_firmware_load_gating_prod,
+                .slcg_fb_load_gating_prod =
+                        gp106_slcg_fb_load_gating_prod,
+                .slcg_fifo_load_gating_prod =
+                        gp106_slcg_fifo_load_gating_prod,
+                .slcg_gr_load_gating_prod =
+                        gr_gp106_slcg_gr_load_gating_prod,
+                .slcg_ltc_load_gating_prod =
+                        ltc_gp106_slcg_ltc_load_gating_prod,
+                .slcg_perf_load_gating_prod =
+                        gp106_slcg_perf_load_gating_prod,
+                .slcg_priring_load_gating_prod =
+                        gp106_slcg_priring_load_gating_prod,
+                .slcg_pmu_load_gating_prod =
+                        gp106_slcg_pmu_load_gating_prod,
+                .slcg_therm_load_gating_prod =
+                        gp106_slcg_therm_load_gating_prod,
+                .slcg_xbar_load_gating_prod =
+                        gp106_slcg_xbar_load_gating_prod,
+                .blcg_bus_load_gating_prod =
+                        gp106_blcg_bus_load_gating_prod,
+                .blcg_ce_load_gating_prod =
+                        gp106_blcg_ce_load_gating_prod,
+                .blcg_fb_load_gating_prod =
+                        gp106_blcg_fb_load_gating_prod,
+                .blcg_fifo_load_gating_prod =
+                        gp106_blcg_fifo_load_gating_prod,
+                .blcg_gr_load_gating_prod =
+                        gp106_blcg_gr_load_gating_prod,
+                .blcg_ltc_load_gating_prod =
+                        gp106_blcg_ltc_load_gating_prod,
+                .blcg_pmu_load_gating_prod =
+                        gp106_blcg_pmu_load_gating_prod,
+                .blcg_xbar_load_gating_prod =
+                        gp106_blcg_xbar_load_gating_prod,
+                .pg_gr_load_gating_prod =
+                        gr_gp106_pg_gr_load_gating_prod,
+                }
+};
+
+static int gp106_get_litter_value(struct gk20a *g, int value)
+{
+        int ret = -EINVAL;
+
+        switch (value) {
+        case GPU_LIT_NUM_GPCS:
+                ret = proj_scal_litter_num_gpcs_v();
+                break;
+        case GPU_LIT_NUM_PES_PER_GPC:
+                ret = proj_scal_litter_num_pes_per_gpc_v();
+                break;
+        case GPU_LIT_NUM_ZCULL_BANKS:
+                ret = proj_scal_litter_num_zcull_banks_v();
+                break;
+        case GPU_LIT_NUM_TPC_PER_GPC:
+                ret = proj_scal_litter_num_tpc_per_gpc_v();
+                break;
+        case GPU_LIT_NUM_FBPS:
+                ret = proj_scal_litter_num_fbps_v();
+                break;
+        case GPU_LIT_GPC_BASE:
+                ret = proj_gpc_base_v();
+                break;
+        case GPU_LIT_GPC_STRIDE:
+                ret = proj_gpc_stride_v();
+                break;
+        case GPU_LIT_GPC_SHARED_BASE:
+                ret = proj_gpc_shared_base_v();
+                break;
+        case GPU_LIT_TPC_IN_GPC_BASE:
+                ret = proj_tpc_in_gpc_base_v();
+                break;
+        case GPU_LIT_TPC_IN_GPC_STRIDE:
+                ret = proj_tpc_in_gpc_stride_v();
+                break;
+        case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+                ret = proj_tpc_in_gpc_shared_base_v();
+                break;
+        case GPU_LIT_PPC_IN_GPC_BASE:
+                ret = proj_ppc_in_gpc_base_v();
+                break;
+        case GPU_LIT_PPC_IN_GPC_STRIDE:
+                ret = proj_ppc_in_gpc_stride_v();
+                break;
+        case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
+                ret = proj_ppc_in_gpc_shared_base_v();
+                break;
+        case GPU_LIT_ROP_BASE:
+                ret = proj_rop_base_v();
+                break;
+        case GPU_LIT_ROP_STRIDE:
+                ret = proj_rop_stride_v();
+                break;
+        case GPU_LIT_ROP_SHARED_BASE:
+                ret = proj_rop_shared_base_v();
+                break;
+        case GPU_LIT_HOST_NUM_ENGINES:
+                ret = proj_host_num_engines_v();
+                break;
+        case GPU_LIT_HOST_NUM_PBDMA:
+                ret = proj_host_num_pbdma_v();
+                break;
+        case GPU_LIT_LTC_STRIDE:
+                ret = proj_ltc_stride_v();
+                break;
+        case GPU_LIT_LTS_STRIDE:
+                ret = proj_lts_stride_v();
+                break;
+        case GPU_LIT_NUM_FBPAS:
+                ret = proj_scal_litter_num_fbpas_v();
+                break;
+        case GPU_LIT_FBPA_SHARED_BASE:
+                ret = proj_fbpa_shared_base_v();
+                break;
+        case GPU_LIT_FBPA_BASE:
+                ret = proj_fbpa_base_v();
+                break;
+        case GPU_LIT_FBPA_STRIDE:
+                ret = proj_fbpa_stride_v();
+                break;
+        default:
+                BUG();
+                break;
+        }
+
+        return ret;
+}
+
+int gp106_init_gpu_characteristics(struct gk20a *g)
+{
+        struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
+
+        int err;
+
+        err = gk20a_init_gpu_characteristics(g);
+        if (err)
+                return err;
+
+        gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE |
+                        NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT |
+                        NVGPU_GPU_FLAGS_SUPPORT_GET_POWER |
+                        NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE;
+
+        return 0;
+}
+
+int gp106_init_hal(struct gk20a *g)
+{
+        struct gpu_ops *gops = &g->ops;
+        struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
+
+        gk20a_dbg_fn("");
+
+        *gops = gp106_ops;
+
+        gops->privsecurity = 1;
+        gops->securegpccs = 1;
+        gops->pmupstate = true;
+        gp10b_init_mc(gops);
+        gp106_init_gr(gops);
+        gp106_init_ltc(gops);
+        gp106_init_fb(gops);
+        gp106_init_fifo(gops);
+        gp10b_init_ce(gops);
+        gp106_init_gr_ctx(gops);
+        gp106_init_mm(gops);
+        gp106_init_pmu_ops(gops);
+        gk20a_init_debug_ops(gops);
+        gk20a_init_dbg_session_ops(gops);
+        gp106_init_clk_ops(gops);
+        gp106_init_clk_arb_ops(gops);
+        gp106_init_regops(gops);
+        gp10b_init_cde_ops(gops);
+        gk20a_init_tsg_ops(gops);
+#if defined(CONFIG_GK20A_CYCLE_STATS)
+        gk20a_init_css_ops(gops);
+#endif
+        gp106_init_bios(gops);
+        gp106_init_therm_ops(gops);
+        gp106_init_xve_ops(gops);
+
+        gops->name = "gp10x";
+        gops->get_litter_value = gp106_get_litter_value;
+        gops->chip_init_gpu_characteristics = gp106_init_gpu_characteristics;
+        gops->gr_ctx.use_dma_for_fw_bootstrap = true;
+        gops->read_ptimer = gk20a_read_ptimer;
+
+        c->twod_class = FERMI_TWOD_A;
+        c->threed_class = PASCAL_B;
+        c->compute_class = PASCAL_COMPUTE_B;
+        c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
+        c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
+        c->dma_copy_class = PASCAL_DMA_COPY_A;
+
+        gk20a_dbg_fn("done");
+
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.h b/drivers/gpu/nvgpu/gp106/hal_gp106.h
new file mode 100644
index 00000000..af91267b
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.h
@@ -0,0 +1,21 @@
+/*
+ * GP106 Tegra HAL interface
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_HAL_GP106_H
+#define _NVGPU_HAL_GP106_H
+struct gk20a;
+
+int gp106_init_hal(struct gk20a *gops);
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_bus_gp106.h b/drivers/gpu/nvgpu/gp106/hw_bus_gp106.h
new file mode 100644
index 00000000..6d80b6a6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_bus_gp106.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gp106_h_
+#define _hw_bus_gp106_h_
+
+static inline u32 bus_bar1_block_r(void)
+{
+        return 0x00001704;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+        return 0x00001714;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 bus_bind_status_r(void)
+{
+        return 0x00001710;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+        return 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+        return 0x2;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+        return 0x4;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+        return 0x8;
+}
+static inline u32 bus_intr_0_r(void)
+{
+        return 0x00001100;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+        return 0x00001140;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+        return 0x1 << 3;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h
new file mode 100644
index 00000000..65146d39
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gp106_h_
+#define _hw_ccsr_gp106_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+        return 0x00800000 + i*8;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+        return 0x00001000;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+        return 0x00800004 + i*8;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+        return 0x00001000;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+        return (v & 0x1) << 10;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+        return 0x400;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+        return 0x800;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+        return (r >> 24) & 0xf;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ce_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ce_gp106.h
new file mode 100644
index 00000000..36311136
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ce_gp106.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce_gp106_h_
+#define _hw_ce_gp106_h_
+
+static inline u32 ce_intr_status_r(u32 i)
+{
+        return 0x00104410 + i*128;
+}
+static inline u32 ce_intr_status_blockpipe_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ce_intr_status_blockpipe_reset_f(void)
+{
+        return 0x1;
+}
+static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
+{
+        return 0x2;
+}
+static inline u32 ce_intr_status_launcherr_pending_f(void)
+{
+        return 0x4;
+}
+static inline u32 ce_intr_status_launcherr_reset_f(void)
+{
+        return 0x4;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h
new file mode 100644
index 00000000..ed3e6009
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ctxsw_prog_gp106.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gp106_h_
+#define _hw_ctxsw_prog_gp106_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+        return 0x00000100;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+        return 0x00000008;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+        return 0x00000010;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+        return 0x00000014;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+        return 0x00000018;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+        return 0x0000001c;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+        return 0x00000020;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+        return 0x00000028;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+        return 0x7 << 0;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+        return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+        return 0x7 << 3;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+        return 0x8;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+        return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+        return 0x0000002c;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+        return 0x000000f4;
+}
+static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
+{
+        return 0x000000d0;
+}
+static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
+{
+        return 0x000000d4;
+}
+static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
+{
+        return 0x000000d8;
+}
+static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
+{
+        return 0x000000dc;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+        return 0x000000f8;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+        return 0x000000fc;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+        return 0x600dc0de;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+        return 0x0000000c;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+        return 0x000000f4;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+        return (r >> 16) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+        return 0x000000f8;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+        return 0x000000fc;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+        return 0xad0becab;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+        return 0x000000ec;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+        return (r >> 16) & 0xff;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+        return 0x00000100;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+        return 0x000000a0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+        return 2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+        return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+        return 0x2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+        return 0x000000a4;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+        return 0x000000a8;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+        return 0x0000003c;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
+{
+        return 0x00000080;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
+{
+        return 0x1;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
+{
+        return 0x00000068;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
+{
+        return 0x00000084;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
+{
+        return 0x1;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
+{
+        return 0x2;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_fb_gp106.h b/drivers/gpu/nvgpu/gp106/hw_fb_gp106.h
new file mode 100644
index 00000000..519679f5
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_fb_gp106.h
@@ -0,0 +1,609 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gp106_h_
+#define _hw_fb_gp106_h_
+
+static inline u32 fb_fbhub_num_active_ltcs_r(void)
+{
+        return 0x00100800;
+}
+static inline u32 fb_mmu_ctrl_r(void)
+{
+        return 0x00100c80;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+        return 0x1;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+        return (r >> 15) & 0x1;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+        return (r >> 16) & 0xff;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
+{
+        return (r >> 11) & 0x1;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
+{
+        return 0x800;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+        return 0x00100ce4;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+        return 0x00100cb8;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+        return 0x2;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+        return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+        return 0x00100cbc;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+        return 0x1;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+        return 0x2;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
+{
+        return 1;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
+{
+        return 0x4;
+}
+static inline u32 fb_mmu_invalidate_replay_s(void)
+{
+        return 3;
+}
+static inline u32 fb_mmu_invalidate_replay_f(u32 v)
+{
+        return (v & 0x7) << 3;
+}
+static inline u32 fb_mmu_invalidate_replay_m(void)
+{
+        return 0x7 << 3;
+}
+static inline u32 fb_mmu_invalidate_replay_v(u32 r)
+{
+        return (r >> 3) & 0x7;
+}
+static inline u32 fb_mmu_invalidate_replay_none_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_invalidate_replay_start_f(void)
+{
+        return 0x8;
+}
+static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
+{
+        return 0x10;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
+{
+        return 0x18;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
+{
+        return 0x20;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
+{
+        return 0x20;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_s(void)
+{
+        return 1;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_m(void)
+{
+        return 0x1 << 6;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
+{
+        return (r >> 6) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
+{
+        return 0x40;
+}
+static inline u32 fb_mmu_invalidate_ack_s(void)
+{
+        return 2;
+}
+static inline u32 fb_mmu_invalidate_ack_f(u32 v)
+{
+        return (v & 0x3) << 7;
+}
+static inline u32 fb_mmu_invalidate_ack_m(void)
+{
+        return 0x3 << 7;
+}
+static inline u32 fb_mmu_invalidate_ack_v(u32 r)
+{
+        return (r >> 7) & 0x3;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
+{
+        return 0x100;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
+{
+        return 0x80;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
+{
+        return 6;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
+{
+        return (v & 0x3f) << 9;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
+{
+        return 0x3f << 9;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
+{
+        return (r >> 9) & 0x3f;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
+{
+        return 5;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
+{
+        return (v & 0x1f) << 15;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
+{
+        return 0x1f << 15;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
+{
+        return (r >> 15) & 0x1f;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
+{
+        return 1;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
+{
+        return (v & 0x1) << 20;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
+{
+        return 0x1 << 20;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
+{
+        return (r >> 20) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
+{
+        return 0x100000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
+{
+        return 3;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
+{
+        return 0x7 << 24;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
+{
+        return (r >> 24) & 0x7;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
+{
+        return 0x2000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
+{
+        return 0x3000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
+{
+        return 0x4000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
+{
+        return 0x5000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
+{
+        return 0x6000000;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
+{
+        return 0x7000000;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+        return 1;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+        return 0x00100cc8;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+        return 2;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+        return 0x2;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+        return 0x4;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+        return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+        return 0x00100ccc;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+        return 0x2;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+        return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+        return 0x00100cc4;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1 << 16;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 fb_mmu_vpr_info_r(void)
+{
+        return 0x00100cd0;
+}
+static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+        return 0x00100c10;
+}
+static inline u32 fb_mmu_local_memory_range_r(void)
+{
+        return 0x00100ce0;
+}
+static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r)
+{
+        return (r >> 0) & 0xf;
+}
+static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r)
+{
+        return (r >> 4) & 0x3f;
+}
+static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 fb_fbpa_fbio_delay_r(void)
+{
+        return 0x9a065c;
+}
+static inline u32 fb_fbpa_fbio_delay_src_m(void)
+{
+        return 0x7;
+}
+static inline u32 fb_fbpa_fbio_delay_src_v(u32 r)
+{
+        return (r >> 0) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_delay_src_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 fb_fbpa_fbio_delay_src_max_v(void)
+{
+        return 2;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_m(void)
+{
+        return 0x7 << 4;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r)
+{
+        return (r >> 4) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_max_v(void)
+{
+        return 2;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_r(void)
+{
+        return 0x9a08e0;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void)
+{
+        return 0x7;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r)
+{
+        return (r >> 0) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void)
+{
+        return 1;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void)
+{
+        return 0x7 << 4;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r)
+{
+        return (r >> 4) & 0x7;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void)
+{
+        return 1;
+}
+static inline u32 fb_niso_scrubber_status_r(void)
+{
+        return 0x00100b20;
+}
+static inline u32 fb_niso_scrubber_status_flag_s(void)
+{
+        return 1;
+}
+static inline u32 fb_niso_scrubber_status_flag_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 fb_niso_scrubber_status_flag_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 fb_niso_scrubber_status_flag_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 fb_niso_scrub_status_r(void)
+{
+        return 0x00100b20;
+}
+static inline u32 fb_niso_scrub_status_flag_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 fb_fbpa_fbio_iref_byte_rx_ctrl_r(void)
+{
+        return 0x009a0eb0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_fbpa_gp106.h b/drivers/gpu/nvgpu/gp106/hw_fbpa_gp106.h
new file mode 100644
index 00000000..7f02eeb6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_fbpa_gp106.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fbpa_gp106_h_
+#define _hw_fbpa_gp106_h_
+
+static inline u32 fbpa_cstatus_r(void)
+{
+        return 0x009a020c;
+}
+static inline u32 fbpa_cstatus_ramamount_v(u32 r)
+{
+        return (r >> 0) & 0x1ffff;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h b/drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h
new file mode 100644
index 00000000..ec02257e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_fifo_gp106.h
@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gp106_h_
+#define _hw_fifo_gp106_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+        return 0x00002254;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+        return 0x00002270;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 fifo_runlist_r(void)
+{
+        return 0x00002274;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+        return (v & 0xf) << 20;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+        return 0x00002280 + i*8;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+        return 0x00000007;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+        return 0x00002284 + i*8;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+        return 0x00000007;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+        return 0x0000ffff;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+        return 0x100000;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+        return 0x00002350 + i*4;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+        return 0x10;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+        return 0x0;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+        return 0x00002390 + i*4;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+        return 0x00002100;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+        return 0x1;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+        return 0x100;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+        return 0x10000;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+        return 0x10000;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
+{
+        return 0x800000;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
+{
+        return 0x800000;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
+{
+        return 0x2000000;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
+{
+        return 0x8000000;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
+{
+        return 0x8000000;
+}
+static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+        return 0x00002140;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+        return 0x1 << 8;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
+{
+        return (v & 0x1) << 28;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_m(void)
+{
+        return 0x1 << 28;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+        return 0x00002528;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+        return 0x0000252c;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+        return 0x0000254c;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
+{
+        return 0x0000000a;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+        return 0x0000256c;
+}
+static inline u32 fifo_intr_mmu_fault_id_r(void)
+{
+        return 0x0000259c;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
+{
+        return 0x0;
+}
+static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
+{
+        return 0x00002800 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
+{
+        return (r >> 0) & 0xfffffff;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
+{
+        return 0x00002804 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
+{
+        return 0x00002808 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
+{
+        return 0x0000280c + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
+{
+        return (r >> 20) & 0x1;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
+{
+        return (r >> 8) & 0x7f;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+        return 0x000025a0;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+        return (v & 0x1) << (0 + i*1);
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+        return 0x00002a00;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+        return 0x00002a04;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+        return 0x3fffffff << 0;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+        return 0x3fffffff;
+}
+static inline u32 fifo_error_sched_disable_r(void)
+{
+        return 0x0000262c;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+        return 0x00002630;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+        return (v & 0x1) << (0 + i*1);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+        return 0x1 << (0 + i*1);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_preempt_r(void)
+{
+        return 0x00002634;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+        return 0x100000;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+        return 0x0;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 fifo_trigger_mmu_fault_r(u32 i)
+{
+        return 0x00002a30 + i*4;
+}
+static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
+{
+        return (v & 0x1f) << 0;
+}
+static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+        return 0x00002640 + i*8;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+        return 0x00000009;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+        return (r >> 0) & 0xfff;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+        return (r >> 12) & 0x1;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+        return (r >> 13) & 0x7;
+}
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+        return 0x00000005;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+        return 0x00000006;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+        return 0x00000007;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+        return (r >> 16) & 0xfff;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+        return (r >> 15) & 0x1;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+        return 0x8000;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+        return 0x00003080 + i*4;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+        return (r >> 0) & 0xfff;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+        return (r >> 12) & 0x1;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+        return (r >> 13) & 0x7;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+        return 0x00000005;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+        return 0x00000006;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+        return 0x00000007;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+        return (r >> 16) & 0xfff;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+        return (r >> 15) & 0x1;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_lo_r(void)
+{
+        return 0x00002a70;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_hi_r(void)
+{
+        return 0x00002a74;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_size_r(void)
+{
+        return 0x00002a78;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
+{
+        return (v & 0x3fff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
+{
+        return 0x00001200;
+}
+static inline u32 fifo_replay_fault_buffer_get_r(void)
+{
+        return 0x00002a7c;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
+{
+        return (v & 0x3fff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_put_r(void)
+{
+        return 0x00002a80;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
+{
+        return (v & 0x3fff) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_r(void)
+{
+        return 0x00002a84;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
+{
+        return (v & 0x1) << 28;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
+{
+        return 0x00000001;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_flush_gp106.h b/drivers/gpu/nvgpu/gp106/hw_flush_gp106.h
new file mode 100644
index 00000000..83bd65bb
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_flush_gp106.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gp106_h_
+#define _hw_flush_gp106_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+        return 0x00070004;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+        return 0x1;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+        return 0x00070010;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+        return 0x0;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+        return 0x1;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+        return 0x0007000c;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+        return 0x0;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+        return 0x1;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+        return 0x00070000;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+        return 0x1;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+        return 0x00000001;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h b/drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h
new file mode 100644
index 00000000..32d8a4f2
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_fuse_gp106.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fuse_gp106_h_
+#define _hw_fuse_gp106_h_
+
+static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021c38 + i*4;
+}
+static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021838 + i*4;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
+{
+        return 0x00021944;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
+{
+        return 0x00021948;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
+{
+        return 0x1;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
+{
+        return 0x0;
+}
+static inline u32 fuse_status_opt_fbio_r(void)
+{
+        return 0x00021c14;
+}
+static inline u32 fuse_status_opt_fbio_data_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 fuse_status_opt_fbio_data_m(void)
+{
+        return 0xffff << 0;
+}
+static inline u32 fuse_status_opt_fbio_data_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
+{
+        return 0x00021d70 + i*4;
+}
+static inline u32 fuse_status_opt_fbp_r(void)
+{
+        return 0x00021d38;
+}
+static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
+{
+        return (r >> (0 + i*0)) & 0x1;
+}
+static inline u32 fuse_vin_cal_fuse_rev_r(void)
+{
+        return 0x0002164c;
+}
+static inline u32 fuse_vin_cal_fuse_rev_v(u32 r)
+{
+        return 0x3 & r;
+}
+static inline u32 fuse_vin_cal_gpc0_r(void)
+{
+        return 0x00021650;
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_data_v(u32 r)
+{
+        return ((r & 0xFFFC000) >> 14);
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_frac_size_v(void)
+{
+        return 2;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_data_v(u32 r)
+{
+        return (r & 0x3FFF);
+}
+static inline u32 fuse_vin_cal_gpc0_slope_frac_size_v(void)
+{
+        return 10;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_r(void)
+{
+        return 0x00021654;
+}
+static inline u32 fuse_vin_cal_gpc1_icpt_sign_f(void)
+{
+        return 0x400000;
+}
+static inline u32 fuse_vin_cal_gpc1_slope_sign_f(void)
+{
+        return 0x800;
+}
+static inline u32 fuse_vin_cal_gpc1_icpt_data_v(u32 r)
+{
+        return ((r & 0x3FF000) >> 12);
+}
+static inline u32 fuse_vin_cal_gpc1_icpt_frac_size_v(void)
+{
+        return 2;
+}
+static inline u32 fuse_vin_cal_gpc1_slope_data_v(u32 r)
+{
+        return (r & 0x7FF);
+}
+static inline u32 fuse_vin_cal_gpc1_slope_frac_size_v(void)
+{
+        return 10;
+}
+static inline u32 fuse_vin_cal_gpc2_delta_r(void)
+{
+        return 0x00021658;
+}
+static inline u32 fuse_vin_cal_gpc3_delta_r(void)
+{
+        return 0x0002165c;
+}
+static inline u32 fuse_vin_cal_gpc4_delta_r(void)
+{
+        return 0x00021660;
+}
+static inline u32 fuse_vin_cal_gpc5_delta_r(void)
+{
+        return 0x00021664;
+}
+static inline u32 fuse_vin_cal_shared_delta_r(void)
+{
+        return 0x00021668;
+}
+static inline u32 fuse_vin_cal_sram_delta_r(void)
+{
+        return 0x0002166c;
+}
+static inline u32 fuse_vin_cal_sram_icpt_data_v(u32 r)
+{
+        return ((r & 0x3FF000) >> 12);
+}
+static inline u32 fuse_vin_cal_sram_icpt_frac_size_v(void)
+{
+        return 1;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_gc6_gp106.h b/drivers/gpu/nvgpu/gp106/hw_gc6_gp106.h
new file mode 100644
index 00000000..25aca9b5
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_gc6_gp106.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gc6_gp106_h_
+#define _hw_gc6_gp106_h_
+static inline u32 gc6_sci_strap_r(void)
+{
+        return 0x00010ebb0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_gmmu_gp106.h b/drivers/gpu/nvgpu/gp106/hw_gmmu_gp106.h
new file mode 100644
index 00000000..96ab77df
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_gmmu_gp106.h
@@ -0,0 +1,1261 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gmmu_gp106_h_
+#define _hw_gmmu_gp106_h_
+
+static inline u32 gmmu_new_pde_is_pte_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pde_is_pte_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_pde_aperture_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pde_aperture_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
+{
+        return 0x2;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
+static inline u32 gmmu_new_pde_address_sys_f(u32 v)
+{
+        return (v & 0xffffff) << 8;
+}
+static inline u32 gmmu_new_pde_address_sys_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pde_vol_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pde_vol_true_f(void)
+{
+        return 0x8;
+}
+static inline u32 gmmu_new_pde_vol_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_pde_address_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 gmmu_new_pde__size_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
+{
+        return 0x2;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
+{
+        return (v & 0xfffffff) << 4;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
+{
+        return 2;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
+{
+        return 0x2;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_w(void)
+{
+        return 2;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
+{
+        return 0x8;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
+{
+        return 0x8;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
+{
+        return (v & 0xffffff) << 8;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
+{
+        return 2;
+}
+static inline u32 gmmu_new_dual_pde_address_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gmmu_new_dual_pde__size_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 gmmu_new_pte__size_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gmmu_new_pte_valid_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pte_valid_true_f(void)
+{
+        return 0x1;
+}
+static inline u32 gmmu_new_pte_valid_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_pte_privilege_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pte_privilege_true_f(void)
+{
+        return 0x20;
+}
+static inline u32 gmmu_new_pte_privilege_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_pte_address_sys_f(u32 v)
+{
+        return (v & 0xffffff) << 8;
+}
+static inline u32 gmmu_new_pte_address_sys_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pte_vol_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pte_vol_true_f(void)
+{
+        return 0x8;
+}
+static inline u32 gmmu_new_pte_vol_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_pte_aperture_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
+{
+        return 0x0;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
+{
+        return 0x4;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6;
+}
+static inline u32 gmmu_new_pte_read_only_w(void)
+{
+        return 0;
+}
+static inline u32 gmmu_new_pte_read_only_true_f(void)
+{
+        return 0x40;
+}
+static inline u32 gmmu_new_pte_comptagline_f(u32 v)
+{
+        return (v & 0x3ffff) << 4;
+}
+static inline u32 gmmu_new_pte_comptagline_w(void)
+{
+        return 1;
+}
+static inline u32 gmmu_new_pte_kind_f(u32 v)
+{
+        return (v & 0xff) << 24;
+}
+static inline u32 gmmu_new_pte_kind_w(void)
+{
+        return 1;
+}
+static inline u32 gmmu_new_pte_address_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 gmmu_pte_kind_f(u32 v)
+{
+        return (v & 0xff) << 4;
+}
+static inline u32 gmmu_pte_kind_w(void)
+{
+        return 1;
+}
+static inline u32 gmmu_pte_kind_invalid_v(void)
+{
+        return 0x000000ff;
+}
+static inline u32 gmmu_pte_kind_pitch_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gmmu_pte_kind_z16_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gmmu_pte_kind_z16_2c_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
+{
+        return 0x00000005;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
+{
+        return 0x00000006;
+}
+static inline u32 gmmu_pte_kind_z16_2z_v(void)
+{
+        return 0x00000007;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
+{
+        return 0x00000009;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
+{
+        return 0x0000000a;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 gmmu_pte_kind_z16_2cz_v(void)
+{
+        return 0x00000036;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
+{
+        return 0x00000037;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
+{
+        return 0x00000038;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
+{
+        return 0x00000039;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
+{
+        return 0x0000005f;
+}
+static inline u32 gmmu_pte_kind_z16_4cz_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
+{
+        return 0x0000000d;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
+{
+        return 0x0000000e;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
+{
+        return 0x0000000f;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 gmmu_pte_kind_s8z24_v(void)
+{
+        return 0x00000011;
+}
+static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
+{
+        return 0x00000012;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
+{
+        return 0x00000013;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
+{
+        return 0x00000014;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
+{
+        return 0x00000015;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
+{
+        return 0x00000016;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
+{
+        return 0x00000017;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
+{
+        return 0x00000018;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
+{
+        return 0x00000019;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
+{
+        return 0x0000001a;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
+{
+        return 0x0000001b;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
+{
+        return 0x0000001c;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
+{
+        return 0x0000001d;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
+{
+        return 0x0000001e;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
+{
+        return 0x0000001f;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
+{
+        return 0x00000020;
+}
+static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
+{
+        return 0x00000021;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
+{
+        return 0x00000022;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
+{
+        return 0x00000023;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
+{
+        return 0x00000024;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
+{
+        return 0x00000025;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
+{
+        return 0x00000026;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
+{
+        return 0x00000027;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
+{
+        return 0x00000028;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
+{
+        return 0x00000029;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
+{
+        return 0x0000002e;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
+{
+        return 0x0000002f;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
+{
+        return 0x00000030;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
+{
+        return 0x00000031;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
+{
+        return 0x00000032;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
+{
+        return 0x00000033;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
+{
+        return 0x00000034;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
+{
+        return 0x00000035;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
+{
+        return 0x0000003a;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
+{
+        return 0x0000003b;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
+{
+        return 0x0000003c;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
+{
+        return 0x0000003d;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
+{
+        return 0x0000003e;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
+{
+        return 0x0000003f;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
+{
+        return 0x00000040;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
+{
+        return 0x00000041;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000042;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000043;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000044;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
+{
+        return 0x00000045;
+}
+static inline u32 gmmu_pte_kind_z24s8_v(void)
+{
+        return 0x00000046;
+}
+static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
+{
+        return 0x00000047;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
+{
+        return 0x00000048;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
+{
+        return 0x00000049;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
+{
+        return 0x0000004a;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
+{
+        return 0x0000004b;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
+{
+        return 0x0000004c;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
+{
+        return 0x0000004d;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
+{
+        return 0x0000004e;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
+{
+        return 0x0000004f;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
+{
+        return 0x00000050;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
+{
+        return 0x00000051;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
+{
+        return 0x00000052;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
+{
+        return 0x00000053;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
+{
+        return 0x00000054;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
+{
+        return 0x00000055;
+}
+static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
+{
+        return 0x00000056;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
+{
+        return 0x00000057;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
+{
+        return 0x00000058;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
+{
+        return 0x00000059;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
+{
+        return 0x0000005a;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
+{
+        return 0x0000005b;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
+{
+        return 0x0000005c;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
+{
+        return 0x0000005d;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
+{
+        return 0x0000005e;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000063;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000064;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000065;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
+{
+        return 0x00000066;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
+{
+        return 0x00000067;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
+{
+        return 0x00000068;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
+{
+        return 0x00000069;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
+{
+        return 0x0000006a;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
+{
+        return 0x0000006f;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
+{
+        return 0x00000070;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
+{
+        return 0x00000071;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
+{
+        return 0x00000072;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
+{
+        return 0x00000073;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
+{
+        return 0x00000074;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
+{
+        return 0x00000075;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
+{
+        return 0x00000076;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000077;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000078;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000079;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
+{
+        return 0x0000007a;
+}
+static inline u32 gmmu_pte_kind_zf32_v(void)
+{
+        return 0x0000007b;
+}
+static inline u32 gmmu_pte_kind_zf32_1z_v(void)
+{
+        return 0x0000007c;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
+{
+        return 0x0000007d;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
+{
+        return 0x0000007e;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
+{
+        return 0x0000007f;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
+{
+        return 0x00000080;
+}
+static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
+{
+        return 0x00000081;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
+{
+        return 0x00000082;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
+{
+        return 0x00000083;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
+{
+        return 0x00000084;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
+{
+        return 0x00000085;
+}
+static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
+{
+        return 0x00000086;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
+{
+        return 0x00000087;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
+{
+        return 0x00000088;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
+{
+        return 0x00000089;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
+{
+        return 0x0000008a;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x0000008b;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x0000008c;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x0000008d;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x0000008e;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x0000008f;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x00000090;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x00000091;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x00000092;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000097;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000098;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000099;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x0000009a;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x0000009b;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x0000009c;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x0000009d;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x0000009e;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x0000009f;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000a0;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000a1;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000a2;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000a3;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000a4;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000a5;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000a6;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x000000a7;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x000000a8;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x000000a9;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x000000aa;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x000000ab;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x000000ac;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x000000ad;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x000000ae;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x000000b3;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x000000b4;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x000000b5;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x000000b6;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x000000b7;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x000000b8;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x000000b9;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x000000ba;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x000000bb;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000bc;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000bd;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000be;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000bf;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000c0;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000c1;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000c2;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
+{
+        return 0x000000c3;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
+{
+        return 0x000000c4;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
+{
+        return 0x000000c5;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
+{
+        return 0x000000c6;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
+{
+        return 0x000000c7;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
+{
+        return 0x000000c8;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
+{
+        return 0x000000ce;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
+{
+        return 0x000000cf;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
+{
+        return 0x000000d0;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
+{
+        return 0x000000d1;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
+{
+        return 0x000000d2;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
+{
+        return 0x000000d3;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
+{
+        return 0x000000d4;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
+{
+        return 0x000000d5;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
+{
+        return 0x000000d6;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
+{
+        return 0x000000d7;
+}
+static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
+{
+        return 0x000000fe;
+}
+static inline u32 gmmu_pte_kind_c32_2c_v(void)
+{
+        return 0x000000d8;
+}
+static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
+{
+        return 0x000000d9;
+}
+static inline u32 gmmu_pte_kind_c32_2cba_v(void)
+{
+        return 0x000000da;
+}
+static inline u32 gmmu_pte_kind_c32_2cra_v(void)
+{
+        return 0x000000db;
+}
+static inline u32 gmmu_pte_kind_c32_2bra_v(void)
+{
+        return 0x000000dc;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
+{
+        return 0x000000dd;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
+{
+        return 0x000000de;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
+{
+        return 0x000000df;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
+{
+        return 0x000000e0;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
+{
+        return 0x000000e1;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
+{
+        return 0x000000e2;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
+{
+        return 0x000000e3;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
+{
+        return 0x0000002c;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
+{
+        return 0x000000e4;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
+{
+        return 0x000000e5;
+}
+static inline u32 gmmu_pte_kind_c64_2c_v(void)
+{
+        return 0x000000e6;
+}
+static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
+{
+        return 0x000000e7;
+}
+static inline u32 gmmu_pte_kind_c64_2cba_v(void)
+{
+        return 0x000000e8;
+}
+static inline u32 gmmu_pte_kind_c64_2cra_v(void)
+{
+        return 0x000000e9;
+}
+static inline u32 gmmu_pte_kind_c64_2bra_v(void)
+{
+        return 0x000000ea;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
+{
+        return 0x000000eb;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
+{
+        return 0x000000ec;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
+{
+        return 0x000000ed;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
+{
+        return 0x000000ee;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
+{
+        return 0x000000ef;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
+{
+        return 0x000000f0;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
+{
+        return 0x000000f1;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
+{
+        return 0x0000002d;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
+{
+        return 0x000000f2;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
+{
+        return 0x000000f3;
+}
+static inline u32 gmmu_pte_kind_c128_2c_v(void)
+{
+        return 0x000000f4;
+}
+static inline u32 gmmu_pte_kind_c128_2cr_v(void)
+{
+        return 0x000000f5;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
+{
+        return 0x000000f6;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
+{
+        return 0x000000f7;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
+{
+        return 0x000000f8;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
+{
+        return 0x000000f9;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
+{
+        return 0x000000fa;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
+{
+        return 0x000000fb;
+}
+static inline u32 gmmu_pte_kind_x8c24_v(void)
+{
+        return 0x000000fc;
+}
+static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
+{
+        return 0x000000fd;
+}
+static inline u32 gmmu_pte_kind_smsked_message_v(void)
+{
+        return 0x000000ca;
+}
+static inline u32 gmmu_pte_kind_smhost_message_v(void)
+{
+        return 0x000000cb;
+}
+static inline u32 gmmu_pte_kind_s8_v(void)
+{
+        return 0x0000002a;
+}
+static inline u32 gmmu_pte_kind_s8_2s_v(void)
+{
+        return 0x0000002b;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h
new file mode 100644
index 00000000..bb1f9fa9
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_gr_gp106.h
@@ -0,0 +1,4017 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gr_gp106_h_
+#define _hw_gr_gp106_h_
+
+static inline u32 gr_intr_r(void)
+{
+        return 0x00400100;
+}
+static inline u32 gr_intr_notify_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_intr_notify_reset_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_intr_semaphore_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_intr_semaphore_reset_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_intr_illegal_method_pending_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_intr_illegal_method_reset_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_intr_illegal_notify_pending_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_intr_illegal_notify_reset_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_intr_illegal_class_pending_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_intr_illegal_class_reset_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_intr_fecs_error_pending_f(void)
+{
+        return 0x80000;
+}
+static inline u32 gr_intr_fecs_error_reset_f(void)
+{
+        return 0x80000;
+}
+static inline u32 gr_intr_class_error_pending_f(void)
+{
+        return 0x100000;
+}
+static inline u32 gr_intr_class_error_reset_f(void)
+{
+        return 0x100000;
+}
+static inline u32 gr_intr_exception_pending_f(void)
+{
+        return 0x200000;
+}
+static inline u32 gr_intr_exception_reset_f(void)
+{
+        return 0x200000;
+}
+static inline u32 gr_fecs_intr_r(void)
+{
+        return 0x00400144;
+}
+static inline u32 gr_class_error_r(void)
+{
+        return 0x00400110;
+}
+static inline u32 gr_class_error_code_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 gr_intr_nonstall_r(void)
+{
+        return 0x00400120;
+}
+static inline u32 gr_intr_nonstall_trap_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_intr_en_r(void)
+{
+        return 0x0040013c;
+}
+static inline u32 gr_exception_r(void)
+{
+        return 0x00400108;
+}
+static inline u32 gr_exception_fe_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_exception_gpc_m(void)
+{
+        return 0x1 << 24;
+}
+static inline u32 gr_exception_memfmt_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_exception_ds_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 gr_exception1_r(void)
+{
+        return 0x00400118;
+}
+static inline u32 gr_exception1_gpc_0_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_exception2_r(void)
+{
+        return 0x0040011c;
+}
+static inline u32 gr_exception_en_r(void)
+{
+        return 0x00400138;
+}
+static inline u32 gr_exception_en_fe_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_exception1_en_r(void)
+{
+        return 0x00400130;
+}
+static inline u32 gr_exception2_en_r(void)
+{
+        return 0x00400134;
+}
+static inline u32 gr_gpfifo_ctl_r(void)
+{
+        return 0x00400500;
+}
+static inline u32 gr_gpfifo_ctl_access_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
+{
+        return (v & 0x1) << 16;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
+{
+        return 0x10000;
+}
+static inline u32 gr_gpfifo_status_r(void)
+{
+        return 0x00400504;
+}
+static inline u32 gr_trapped_addr_r(void)
+{
+        return 0x00400704;
+}
+static inline u32 gr_trapped_addr_mthd_v(u32 r)
+{
+        return (r >> 2) & 0xfff;
+}
+static inline u32 gr_trapped_addr_subch_v(u32 r)
+{
+        return (r >> 16) & 0x7;
+}
+static inline u32 gr_trapped_data_lo_r(void)
+{
+        return 0x00400708;
+}
+static inline u32 gr_trapped_data_hi_r(void)
+{
+        return 0x0040070c;
+}
+static inline u32 gr_status_r(void)
+{
+        return 0x00400700;
+}
+static inline u32 gr_status_fe_method_upper_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 gr_status_fe_method_lower_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 gr_status_fe_method_lower_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_status_fe_gi_v(u32 r)
+{
+        return (r >> 21) & 0x1;
+}
+static inline u32 gr_status_mask_r(void)
+{
+        return 0x00400610;
+}
+static inline u32 gr_status_1_r(void)
+{
+        return 0x00400604;
+}
+static inline u32 gr_status_2_r(void)
+{
+        return 0x00400608;
+}
+static inline u32 gr_engine_status_r(void)
+{
+        return 0x0040060c;
+}
+static inline u32 gr_engine_status_value_busy_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450c;
+}
+static inline u32 gr_activity_0_r(void)
+{
+        return 0x00400380;
+}
+static inline u32 gr_activity_1_r(void)
+{
+        return 0x00400384;
+}
+static inline u32 gr_activity_2_r(void)
+{
+        return 0x00400388;
+}
+static inline u32 gr_activity_4_r(void)
+{
+        return 0x00400390;
+}
+static inline u32 gr_activity_4_gpc0_s(void)
+{
+        return 3;
+}
+static inline u32 gr_activity_4_gpc0_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_activity_4_gpc0_m(void)
+{
+        return 0x7 << 0;
+}
+static inline u32 gr_activity_4_gpc0_v(u32 r)
+{
+        return (r >> 0) & 0x7;
+}
+static inline u32 gr_activity_4_gpc0_empty_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_activity_4_gpc0_preempted_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
+{
+        return 0x00501000;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
+{
+        return 0x00419000;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
+{
+        return 0x005046a4;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
+{
+        return 0x00419ea4;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_pri_sked_activity_r(void)
+{
+        return 0x00407054;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
+{
+        return 0x00502c80;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
+{
+        return 0x00502c84;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
+{
+        return 0x00502c88;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
+{
+        return 0x00502c8c;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504500;
+}
+static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504d00;
+}
+static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00501d00;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
+{
+        return 0x0041ac80;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
+{
+        return 0x0041ac84;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
+{
+        return 0x0041ac88;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
+{
+        return 0x0041ac8c;
+}
+static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041c500;
+}
+static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041cd00;
+}
+static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00419d00;
+}
+static inline u32 gr_pri_be0_becs_be_activity0_r(void)
+{
+        return 0x00410200;
+}
+static inline u32 gr_pri_be1_becs_be_activity0_r(void)
+{
+        return 0x00410600;
+}
+static inline u32 gr_pri_bes_becs_be_activity0_r(void)
+{
+        return 0x00408a00;
+}
+static inline u32 gr_pri_ds_mpipe_status_r(void)
+{
+        return 0x00405858;
+}
+static inline u32 gr_pri_fe_go_idle_info_r(void)
+{
+        return 0x00404194;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
+{
+        return 0x00504238;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
+{
+        return 0x005046b8;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
+{
+        return 0x80;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
+{
+        return 0x200;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
+{
+        return 0x400;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
+{
+        return 0x800;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
+{
+        return 0x005044a0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
+{
+        return 0x200;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
+{
+        return 0x005046bc;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
+{
+        return 0x005046c0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
+{
+        return 0x005044a4;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
+{
+        return 0xff << 0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
+{
+        return 0xff << 8;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
+{
+        return (r >> 8) & 0xff;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
+{
+        return 0xff << 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
+{
+        return (r >> 16) & 0xff;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
+{
+        return 0x005042c4;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_pri_be0_crop_status1_r(void)
+{
+        return 0x00410134;
+}
+static inline u32 gr_pri_bes_crop_status1_r(void)
+{
+        return 0x00408934;
+}
+static inline u32 gr_pri_be0_zrop_status_r(void)
+{
+        return 0x00410048;
+}
+static inline u32 gr_pri_be0_zrop_status2_r(void)
+{
+        return 0x0041004c;
+}
+static inline u32 gr_pri_bes_zrop_status_r(void)
+{
+        return 0x00408848;
+}
+static inline u32 gr_pri_bes_zrop_status2_r(void)
+{
+        return 0x0040884c;
+}
+static inline u32 gr_pipe_bundle_address_r(void)
+{
+        return 0x00400200;
+}
+static inline u32 gr_pipe_bundle_address_value_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 gr_pipe_bundle_data_r(void)
+{
+        return 0x00400204;
+}
+static inline u32 gr_pipe_bundle_config_r(void)
+{
+        return 0x00400208;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_fe_hww_esr_r(void)
+{
+        return 0x00404000;
+}
+static inline u32 gr_fe_hww_esr_reset_active_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_fe_hww_esr_en_enable_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_fe_go_idle_timeout_r(void)
+{
+        return 0x00404154;
+}
+static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
+{
+        return 0x1800;
+}
+static inline u32 gr_fe_object_table_r(u32 i)
+{
+        return 0x00404200 + i*4;
+}
+static inline u32 gr_fe_object_table_nvclass_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 gr_fe_tpc_fs_r(void)
+{
+        return 0x004041c4;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_r(void)
+{
+        return 0x00404488;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_pri_mme_shadow_raw_data_r(void)
+{
+        return 0x0040448c;
+}
+static inline u32 gr_mme_hww_esr_r(void)
+{
+        return 0x00404490;
+}
+static inline u32 gr_mme_hww_esr_reset_active_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_mme_hww_esr_en_enable_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_memfmt_hww_esr_r(void)
+{
+        return 0x00404600;
+}
+static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_fecs_cpuctl_r(void)
+{
+        return 0x00409100;
+}
+static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 gr_fecs_cpuctl_alias_r(void)
+{
+        return 0x00409130;
+}
+static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 gr_fecs_dmactl_r(void)
+{
+        return 0x0040910c;
+}
+static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 gr_fecs_os_r(void)
+{
+        return 0x00409080;
+}
+static inline u32 gr_fecs_idlestate_r(void)
+{
+        return 0x0040904c;
+}
+static inline u32 gr_fecs_mailbox0_r(void)
+{
+        return 0x00409040;
+}
+static inline u32 gr_fecs_mailbox1_r(void)
+{
+        return 0x00409044;
+}
+static inline u32 gr_fecs_irqstat_r(void)
+{
+        return 0x00409008;
+}
+static inline u32 gr_fecs_irqmode_r(void)
+{
+        return 0x0040900c;
+}
+static inline u32 gr_fecs_irqmask_r(void)
+{
+        return 0x00409018;
+}
+static inline u32 gr_fecs_irqdest_r(void)
+{
+        return 0x0040901c;
+}
+static inline u32 gr_fecs_curctx_r(void)
+{
+        return 0x00409050;
+}
+static inline u32 gr_fecs_nxtctx_r(void)
+{
+        return 0x00409054;
+}
+static inline u32 gr_fecs_engctl_r(void)
+{
+        return 0x004090a4;
+}
+static inline u32 gr_fecs_debug1_r(void)
+{
+        return 0x00409090;
+}
+static inline u32 gr_fecs_debuginfo_r(void)
+{
+        return 0x00409094;
+}
+static inline u32 gr_fecs_icd_cmd_r(void)
+{
+        return 0x00409200;
+}
+static inline u32 gr_fecs_icd_cmd_opc_s(void)
+{
+        return 4;
+}
+static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 gr_fecs_icd_cmd_opc_m(void)
+{
+        return 0xf << 0;
+}
+static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0) & 0xf;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
+{
+        return 0xe;
+}
+static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1f) << 8;
+}
+static inline u32 gr_fecs_icd_rdata_r(void)
+{
+        return 0x0040920c;
+}
+static inline u32 gr_fecs_imemc_r(u32 i)
+{
+        return 0x00409180 + i*16;
+}
+static inline u32 gr_fecs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 gr_fecs_imemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_fecs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 gr_fecs_imemd_r(u32 i)
+{
+        return 0x00409184 + i*16;
+}
+static inline u32 gr_fecs_imemt_r(u32 i)
+{
+        return 0x00409188 + i*16;
+}
+static inline u32 gr_fecs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_fecs_dmemc_r(u32 i)
+{
+        return 0x004091c0 + i*8;
+}
+static inline u32 gr_fecs_dmemc_offs_s(void)
+{
+        return 6;
+}
+static inline u32 gr_fecs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 gr_fecs_dmemc_offs_m(void)
+{
+        return 0x3f << 2;
+}
+static inline u32 gr_fecs_dmemc_offs_v(u32 r)
+{
+        return (r >> 2) & 0x3f;
+}
+static inline u32 gr_fecs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 gr_fecs_dmemd_r(u32 i)
+{
+        return 0x004091c4 + i*8;
+}
+static inline u32 gr_fecs_dmatrfbase_r(void)
+{
+        return 0x00409110;
+}
+static inline u32 gr_fecs_dmatrfmoffs_r(void)
+{
+        return 0x00409114;
+}
+static inline u32 gr_fecs_dmatrffboffs_r(void)
+{
+        return 0x0040911c;
+}
+static inline u32 gr_fecs_dmatrfcmd_r(void)
+{
+        return 0x00409118;
+}
+static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_fecs_bootvec_r(void)
+{
+        return 0x00409104;
+}
+static inline u32 gr_fecs_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_falcon_hwcfg_r(void)
+{
+        return 0x00409108;
+}
+static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
+{
+        return 0x0041a108;
+}
+static inline u32 gr_fecs_falcon_rm_r(void)
+{
+        return 0x00409084;
+}
+static inline u32 gr_fecs_current_ctx_r(void)
+{
+        return 0x00409b00;
+}
+static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
+{
+        return (r >> 0) & 0xfffffff;
+}
+static inline u32 gr_fecs_current_ctx_target_s(void)
+{
+        return 2;
+}
+static inline u32 gr_fecs_current_ctx_target_f(u32 v)
+{
+        return (v & 0x3) << 28;
+}
+static inline u32 gr_fecs_current_ctx_target_m(void)
+{
+        return 0x3 << 28;
+}
+static inline u32 gr_fecs_current_ctx_target_v(u32 r)
+{
+        return (r >> 28) & 0x3;
+}
+static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 gr_fecs_current_ctx_valid_s(void)
+{
+        return 1;
+}
+static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 gr_fecs_current_ctx_valid_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 gr_fecs_current_ctx_valid_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_method_data_r(void)
+{
+        return 0x00409500;
+}
+static inline u32 gr_fecs_method_push_r(void)
+{
+        return 0x00409504;
+}
+static inline u32 gr_fecs_method_push_adr_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
+{
+        return 0x3;
+}
+static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
+{
+        return 0x00000009;
+}
+static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
+{
+        return 0x00000015;
+}
+static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
+{
+        return 0x00000016;
+}
+static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
+{
+        return 0x00000025;
+}
+static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
+{
+        return 0x00000030;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
+{
+        return 0x00000031;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
+{
+        return 0x00000032;
+}
+static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
+{
+        return 0x00000038;
+}
+static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
+{
+        return 0x00000039;
+}
+static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
+{
+        return 0x21;
+}
+static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
+{
+        return 0x0000001a;
+}
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 gr_fecs_host_int_status_r(void)
+{
+        return 0x00409c18;
+}
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 16;
+}
+static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
+{
+        return (v & 0x1) << 17;
+}
+static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
+{
+        return (v & 0x1) << 18;
+}
+static inline u32 gr_fecs_host_int_clear_r(void)
+{
+        return 0x00409c20;
+}
+static inline u32 gr_fecs_host_int_enable_r(void)
+{
+        return 0x00409c24;
+}
+static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
+{
+        return 0x10000;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
+{
+        return 0x20000;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
+{
+        return 0x40000;
+}
+static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
+{
+        return 0x80000;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
+{
+        return 0x00409614;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
+{
+        return 0x200;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
+{
+        return 1;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
+{
+        return (v & 0x1) << 10;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
+{
+        return 0x1 << 10;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
+{
+        return (r >> 10) & 0x1;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
+{
+        return 0x400;
+}
+static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
+{
+        return 0x0040960c;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x00409800 + i*4;
+}
+static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
+{
+        return 0x004098c0 + i*4;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
+{
+        return 0x00409840 + i*4;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_fs_r(void)
+{
+        return 0x00409604;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
+{
+        return 5;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
+{
+        return (v & 0x1f) << 0;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
+{
+        return 0x1f << 0;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_s(void)
+{
+        return 5;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
+{
+        return (v & 0x1f) << 16;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_m(void)
+{
+        return 0x1f << 16;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
+{
+        return (r >> 16) & 0x1f;
+}
+static inline u32 gr_fecs_cfg_r(void)
+{
+        return 0x00409620;
+}
+static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 gr_fecs_rc_lanes_r(void)
+{
+        return 0x00409880;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
+{
+        return 6;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3f) << 0;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
+{
+        return 0x3f << 0;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0) & 0x3f;
+}
+static inline u32 gr_fecs_ctxsw_status_1_r(void)
+{
+        return 0x00409400;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
+{
+        return 1;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
+{
+        return (v & 0x1) << 12;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
+{
+        return 0x1 << 12;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
+{
+        return (r >> 12) & 0x1;
+}
+static inline u32 gr_fecs_arb_ctx_adr_r(void)
+{
+        return 0x00409a24;
+}
+static inline u32 gr_fecs_new_ctx_r(void)
+{
+        return 0x00409b04;
+}
+static inline u32 gr_fecs_new_ctx_ptr_s(void)
+{
+        return 28;
+}
+static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_fecs_new_ctx_ptr_m(void)
+{
+        return 0xfffffff << 0;
+}
+static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
+{
+        return (r >> 0) & 0xfffffff;
+}
+static inline u32 gr_fecs_new_ctx_target_s(void)
+{
+        return 2;
+}
+static inline u32 gr_fecs_new_ctx_target_f(u32 v)
+{
+        return (v & 0x3) << 28;
+}
+static inline u32 gr_fecs_new_ctx_target_m(void)
+{
+        return 0x3 << 28;
+}
+static inline u32 gr_fecs_new_ctx_target_v(u32 r)
+{
+        return (r >> 28) & 0x3;
+}
+static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 gr_fecs_new_ctx_valid_s(void)
+{
+        return 1;
+}
+static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 gr_fecs_new_ctx_valid_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_r(void)
+{
+        return 0x00409a0c;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
+{
+        return 28;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
+{
+        return 0xfffffff << 0;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
+{
+        return (r >> 0) & 0xfffffff;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
+{
+        return 2;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
+{
+        return (v & 0x3) << 28;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
+{
+        return 0x3 << 28;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
+{
+        return (r >> 28) & 0x3;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_r(void)
+{
+        return 0x00409a10;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
+{
+        return 5;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
+{
+        return (v & 0x1f) << 0;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
+{
+        return 0x1f << 0;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
+{
+        return 0x00409c00;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
+{
+        return 0x00502c04;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
+{
+        return 0x00502400;
+}
+static inline u32 gr_fecs_ctxsw_idlestate_r(void)
+{
+        return 0x00409420;
+}
+static inline u32 gr_fecs_feature_override_ecc_r(void)
+{
+        return 0x00409658;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
+{
+        return 0x00502420;
+}
+static inline u32 gr_rstr2d_gpc_map0_r(void)
+{
+        return 0x0040780c;
+}
+static inline u32 gr_rstr2d_gpc_map1_r(void)
+{
+        return 0x00407810;
+}
+static inline u32 gr_rstr2d_gpc_map2_r(void)
+{
+        return 0x00407814;
+}
+static inline u32 gr_rstr2d_gpc_map3_r(void)
+{
+        return 0x00407818;
+}
+static inline u32 gr_rstr2d_gpc_map4_r(void)
+{
+        return 0x0040781c;
+}
+static inline u32 gr_rstr2d_gpc_map5_r(void)
+{
+        return 0x00407820;
+}
+static inline u32 gr_rstr2d_map_table_cfg_r(void)
+{
+        return 0x004078bc;
+}
+static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_pd_hww_esr_r(void)
+{
+        return 0x00406018;
+}
+static inline u32 gr_pd_hww_esr_reset_active_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_pd_hww_esr_en_enable_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00406028 + i*4;
+}
+static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
+{
+        return (v & 0xf) << 4;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
+{
+        return (v & 0xf) << 8;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
+{
+        return (v & 0xf) << 12;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
+{
+        return (v & 0xf) << 16;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
+{
+        return (v & 0xf) << 20;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
+{
+        return (v & 0xf) << 24;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
+{
+        return (v & 0xf) << 28;
+}
+static inline u32 gr_pd_ab_dist_cfg0_r(void)
+{
+        return 0x004064c0;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_pd_ab_dist_cfg1_r(void)
+{
+        return 0x004064c4;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
+{
+        return 0xffff;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
+{
+        return (v & 0xffff) << 16;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
+{
+        return 0x00000080;
+}
+static inline u32 gr_pd_ab_dist_cfg2_r(void)
+{
+        return 0x004064c8;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
+{
+        return (v & 0x1fff) << 0;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
+{
+        return 0x00000900;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
+{
+        return (v & 0x1fff) << 16;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
+{
+        return 0x00000020;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
+{
+        return 0x00000900;
+}
+static inline u32 gr_pd_dist_skip_table_r(u32 i)
+{
+        return 0x004064d0 + i*4;
+}
+static inline u32 gr_pd_dist_skip_table__size_1_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xff) << 16;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xff) << 24;
+}
+static inline u32 gr_ds_debug_r(void)
+{
+        return 0x00405800;
+}
+static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
+{
+        return 0x8000000;
+}
+static inline u32 gr_ds_zbc_color_r_r(void)
+{
+        return 0x00405804;
+}
+static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_g_r(void)
+{
+        return 0x00405808;
+}
+static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_b_r(void)
+{
+        return 0x0040580c;
+}
+static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_a_r(void)
+{
+        return 0x00405810;
+}
+static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_fmt_r(void)
+{
+        return 0x00405814;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
+{
+        return (v & 0x7f) << 0;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028;
+}
+static inline u32 gr_ds_zbc_z_r(void)
+{
+        return 0x00405818;
+}
+static inline u32 gr_ds_zbc_z_val_s(void)
+{
+        return 32;
+}
+static inline u32 gr_ds_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_z_val_m(void)
+{
+        return 0xffffffff << 0;
+}
+static inline u32 gr_ds_zbc_z_val_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 gr_ds_zbc_z_val__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_ds_zbc_z_val__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_ds_zbc_z_fmt_r(void)
+{
+        return 0x0040581c;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_ds_zbc_tbl_index_r(void)
+{
+        return 0x00405820;
+}
+static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 gr_ds_zbc_tbl_ld_r(void)
+{
+        return 0x00405824;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
+{
+        return 0x4;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
+{
+        return 0x00405830;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
+{
+        return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
+{
+        return 0x0040585c;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_ds_hww_esr_r(void)
+{
+        return 0x00405840;
+}
+static inline u32 gr_ds_hww_esr_reset_s(void)
+{
+        return 1;
+}
+static inline u32 gr_ds_hww_esr_reset_f(u32 v)
+{
+        return (v & 0x1) << 30;
+}
+static inline u32 gr_ds_hww_esr_reset_m(void)
+{
+        return 0x1 << 30;
+}
+static inline u32 gr_ds_hww_esr_reset_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 gr_ds_hww_esr_reset_task_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_ds_hww_esr_reset_task_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_ds_hww_esr_en_enabled_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_ds_hww_esr_2_r(void)
+{
+        return 0x00405848;
+}
+static inline u32 gr_ds_hww_esr_2_reset_s(void)
+{
+        return 1;
+}
+static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
+{
+        return (v & 0x1) << 30;
+}
+static inline u32 gr_ds_hww_esr_2_reset_m(void)
+{
+        return 0x1 << 30;
+}
+static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_ds_hww_report_mask_r(void)
+{
+        return 0x00405844;
+}
+static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
+{
+        return 0x4;
+}
+static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
+{
+        return 0x80;
+}
+static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
+{
+        return 0x200;
+}
+static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
+{
+        return 0x400;
+}
+static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
+{
+        return 0x800;
+}
+static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
+{
+        return 0x1000;
+}
+static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
+{
+        return 0x2000;
+}
+static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
+{
+        return 0x4000;
+}
+static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
+{
+        return 0x8000;
+}
+static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
+{
+        return 0x10000;
+}
+static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
+{
+        return 0x20000;
+}
+static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
+{
+        return 0x40000;
+}
+static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
+{
+        return 0x80000;
+}
+static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
+{
+        return 0x100000;
+}
+static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
+{
+        return 0x200000;
+}
+static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
+{
+        return 0x400000;
+}
+static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
+{
+        return 0x800000;
+}
+static inline u32 gr_ds_hww_report_mask_2_r(void)
+{
+        return 0x0040584c;
+}
+static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00405870 + i*4;
+}
+static inline u32 gr_scc_bundle_cb_base_r(void)
+{
+        return 0x00408004;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gr_scc_bundle_cb_size_r(void)
+{
+        return 0x00408008;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ff) << 0;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
+{
+        return 0x00000030;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
+{
+        return 0x00000100;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_scc_pagepool_base_r(void)
+{
+        return 0x0040800c;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gr_scc_pagepool_r(void)
+{
+        return 0x00408010;
+}
+static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ff) << 0;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
+{
+        return 0x00000200;
+}
+static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
+{
+        return 0x00000100;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
+{
+        return 10;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
+{
+        return (v & 0x3ff) << 10;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
+{
+        return 0x3ff << 10;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
+{
+        return (r >> 10) & 0x3ff;
+}
+static inline u32 gr_scc_pagepool_valid_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_scc_init_r(void)
+{
+        return 0x0040802c;
+}
+static inline u32 gr_scc_init_ram_trigger_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_scc_hww_esr_r(void)
+{
+        return 0x00408030;
+}
+static inline u32 gr_scc_hww_esr_reset_active_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_scc_hww_esr_en_enable_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_sked_hww_esr_r(void)
+{
+        return 0x00407020;
+}
+static inline u32 gr_sked_hww_esr_reset_active_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_cwd_fs_r(void)
+{
+        return 0x00405b00;
+}
+static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
+{
+        return 0x00405b60 + i*4;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
+{
+        return (v & 0xf) << 8;
+}
+static inline u32 gr_cwd_sm_id_r(u32 i)
+{
+        return 0x00405ba0 + i*4;
+}
+static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_gpc0_fs_gpc_r(void)
+{
+        return 0x00502608;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
+{
+        return (r >> 16) & 0x1f;
+}
+static inline u32 gr_gpc0_cfg_r(void)
+{
+        return 0x00502620;
+}
+static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 gr_gpccs_rc_lanes_r(void)
+{
+        return 0x00502880;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
+{
+        return 6;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3f) << 0;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
+{
+        return 0x3f << 0;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0) & 0x3f;
+}
+static inline u32 gr_gpccs_rc_lane_size_r(void)
+{
+        return 0x00502910;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_s(void)
+{
+        return 24;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
+{
+        return (v & 0xffffff) << 0;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_m(void)
+{
+        return 0xffffff << 0;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
+{
+        return (r >> 0) & 0xffffff;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_zcull_fs_r(void)
+{
+        return 0x00500910;
+}
+static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
+{
+        return (v & 0x1ff) << 0;
+}
+static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
+{
+        return (v & 0xf) << 16;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_r(void)
+{
+        return 0x00500914;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
+{
+        return (v & 0xf) << 8;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
+{
+        return 0x00500918;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffff) << 0;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
+{
+        return 0x00800000;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
+{
+        return 0x00500920;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
+{
+        return 0x00500a04 + i*32;
+}
+static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
+{
+        return 0x00000040;
+}
+static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
+{
+        return 0x00500c10 + i*4;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
+{
+        return 0x00500c30 + i*4;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
+{
+        return 0x00504088;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
+{
+        return 0x00504698;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
+{
+        return 0x0050469c;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
+{
+        return (r >> 8) & 0xfff;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
+{
+        return (r >> 20) & 0xfff;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
+{
+        return 0x00503018;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
+{
+        return 0x005030c0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
+{
+        return 0x3fffff << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
+{
+        return 0x00000320;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
+{
+        return 0x00000ba8;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
+{
+        return 0x00000020;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
+{
+        return 0x005030f4;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
+{
+        return 0x005030e4;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
+{
+        return 0xffff << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
+{
+        return 0x00000800;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
+{
+        return 0x00000020;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
+{
+        return 0x005030f8;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
+{
+        return 0x005030f0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
+{
+        return 0x00000320;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
+{
+        return 0x00419b00;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
+{
+        return 0x00419b04;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
+{
+        return 21;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
+{
+        return (v & 0x1fffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
+{
+        return 0x1fffff << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
+{
+        return (r >> 0) & 0x1fffff;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
+{
+        return 0x80;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
+{
+        return 1;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_gpccs_falcon_addr_r(void)
+{
+        return 0x0041a0ac;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
+{
+        return 6;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
+{
+        return (v & 0x3f) << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
+{
+        return 0x3f << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
+{
+        return (r >> 0) & 0x3f;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_s(void)
+{
+        return 6;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
+{
+        return (v & 0x3f) << 6;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_m(void)
+{
+        return 0x3f << 6;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
+{
+        return (r >> 6) & 0x3f;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_s(void)
+{
+        return 12;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_m(void)
+{
+        return 0xfff << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
+{
+        return (r >> 0) & 0xfff;
+}
+static inline u32 gr_gpccs_cpuctl_r(void)
+{
+        return 0x0041a100;
+}
+static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 gr_gpccs_dmactl_r(void)
+{
+        return 0x0041a10c;
+}
+static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 gr_gpccs_imemc_r(u32 i)
+{
+        return 0x0041a180 + i*16;
+}
+static inline u32 gr_gpccs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 gr_gpccs_imemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 gr_gpccs_imemd_r(u32 i)
+{
+        return 0x0041a184 + i*16;
+}
+static inline u32 gr_gpccs_imemt_r(u32 i)
+{
+        return 0x0041a188 + i*16;
+}
+static inline u32 gr_gpccs_imemt__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 gr_gpccs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpccs_dmemc_r(u32 i)
+{
+        return 0x0041a1c0 + i*8;
+}
+static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 gr_gpccs_dmemd_r(u32 i)
+{
+        return 0x0041a1c4 + i*8;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x0041a800 + i*4;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
+{
+        return 0x00418e24;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
+{
+        return 32;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
+{
+        return 0xffffffff << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
+{
+        return 0x00418e28;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
+{
+        return 11;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ff) << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
+{
+        return 0x7ff << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
+{
+        return (r >> 0) & 0x7ff;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
+{
+        return 0x00000030;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
+{
+        return 0x30;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
+{
+        return 1;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
+{
+        return 0x005001dc;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
+{
+        return 0x00000de0;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
+{
+        return 0x00000100;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
+{
+        return 0x005001d8;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
+{
+        return 0x004181e4;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
+{
+        return 0x00000100;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
+{
+        return 0x0041befc;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
+{
+        return 0x00418ea0 + i*4;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
+{
+        return 0x3fffff << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
+{
+        return 0x00418010 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
+{
+        return 0x0041804c + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
+{
+        return 0x00418088 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
+{
+        return 0x004180c4 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
+{
+        return 0x00500100;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
+{
+        return 0x00418110 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
+{
+        return 0x0050014c;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
+{
+        return 0x00418810;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_crstr_gpc_map0_r(void)
+{
+        return 0x00418b08;
+}
+static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map1_r(void)
+{
+        return 0x00418b0c;
+}
+static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map2_r(void)
+{
+        return 0x00418b10;
+}
+static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map3_r(void)
+{
+        return 0x00418b14;
+}
+static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map4_r(void)
+{
+        return 0x00418b18;
+}
+static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map5_r(void)
+{
+        return 0x00418b1c;
+}
+static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+{
+        return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+{
+        return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+{
+        return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+{
+        return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_map_table_cfg_r(void)
+{
+        return 0x00418bb8;
+}
+static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
+{
+        return 0x00418980;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
+{
+        return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
+{
+        return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
+{
+        return 0x00418984;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
+{
+        return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
+{
+        return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
+{
+        return 0x00418988;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
+{
+        return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
+{
+        return 3;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
+{
+        return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
+{
+        return 0x7 << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
+{
+        return (r >> 28) & 0x7;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+{
+        return 0x0041898c;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
+{
+        return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
+{
+        return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
+{
+        return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
+{
+        return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
+{
+        return 0x00418c6c;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
+{
+        return 0x00419004;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_gcc_pagepool_r(void)
+{
+        return 0x00419008;
+}
+static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
+{
+        return 0x0041980c;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
+{
+        return 0x00419848;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1) << 28;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
+{
+        return 0x00419c00;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
+{
+        return 0x00419c2c;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1) << 28;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00419e44;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+{
+        return 0x4;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
+{
+        return 0x80;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+{
+        return 0x200;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
+{
+        return 0x400;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+{
+        return 0x800;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
+{
+        return 0x1000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
+{
+        return 0x2000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
+{
+        return 0x4000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+{
+        return 0x8000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+{
+        return 0x10000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
+{
+        return 0x20000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+{
+        return 0x40000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+{
+        return 0x800000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+{
+        return 0x400000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
+{
+        return 0x80000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
+{
+        return 0x100000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419e4c;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+{
+        return 0x4;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
+{
+        return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
+{
+        return 0x00419d0c;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450c;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
+{
+        return 0x0041ac94;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
+{
+        return (v & 0xff) << 16;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
+{
+        return (r >> 16) & 0xff;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
+{
+        return 0x00504610;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
+{
+        return 0x00504614;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00504624;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
+{
+        return 0x00504634;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00419e24;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_warp_disable_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_sm_disable_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
+{
+        return 0x0050460c;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+{
+        return 0x00419e50;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
+{
+        return 0x00504650;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+        return 0x00504224;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
+{
+        return 0x00504648;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
+{
+        return 0x00504770;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
+{
+        return 0x00419f70;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
+{
+        return 0x0050477c;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
+{
+        return 0x00419f7c;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
+{
+        return 0x0041be08;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
+{
+        return 0x4;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+{
+        return 0x0041bf00;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
+{
+        return 0x0041bf04;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
+{
+        return 0x0041bf08;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
+{
+        return 0x0041bf0c;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
+{
+        return 0x0041bf10;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
+{
+        return 0x0041bf14;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
+{
+        return 0x0041bfd0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
+{
+        return (v & 0x1f) << 16;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
+{
+        return (v & 0x7) << 21;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 24;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
+{
+        return 0x0041bfd4;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffff) << 0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
+{
+        return 0x0041bfe4;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 5;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 10;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 15;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 20;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+{
+        return (v & 0x1f) << 25;
+}
+static inline u32 gr_bes_zrop_settings_r(void)
+{
+        return 0x00408850;
+}
+static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 gr_be0_crop_debug3_r(void)
+{
+        return 0x00410108;
+}
+static inline u32 gr_bes_crop_debug3_r(void)
+{
+        return 0x00408908;
+}
+static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_bes_crop_settings_r(void)
+{
+        return 0x00408958;
+}
+static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
+{
+        return 0x00000020;
+}
+static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
+{
+        return 0x00000020;
+}
+static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
+{
+        return 0x000000c0;
+}
+static inline u32 gr_zcull_subregion_qty_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
+{
+        return 0x00504604;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
+{
+        return 0x00504608;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
+{
+        return 0x0050465c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
+{
+        return 0x00504660;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
+{
+        return 0x00504664;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
+{
+        return 0x00504668;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
+{
+        return 0x0050466c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
+{
+        return 0x00504658;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
+{
+        return 0x00504730;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
+{
+        return 0x00504734;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
+{
+        return 0x00504738;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
+{
+        return 0x0050473c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
+{
+        return 0x00504740;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
+{
+        return 0x00504744;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
+{
+        return 0x00504748;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
+{
+        return 0x0050474c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
+{
+        return 0x00504678;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+{
+        return 0x00504694;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
+{
+        return 0x005046f0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
+{
+        return 0x00504700;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
+{
+        return 0x005046f4;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
+{
+        return 0x00504704;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
+{
+        return 0x005046f8;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
+{
+        return 0x00504708;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
+{
+        return 0x005046fc;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
+{
+        return 0x0050470c;
+}
+static inline u32 gr_fe_pwr_mode_r(void)
+{
+        return 0x00404170;
+}
+static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_fe_pwr_mode_req_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 gr_fe_pwr_mode_req_send_f(void)
+{
+        return 0x10;
+}
+static inline u32 gr_fe_pwr_mode_req_done_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
+{
+        return 0x00418880;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
+{
+        return 0x1 << 11;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
+{
+        return 0x3 << 3;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
+{
+        return 0x3 << 5;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
+{
+        return 0x3 << 28;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
+{
+        return 0x1 << 30;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
+{
+        return 0x00418890;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
+{
+        return 0x00418894;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
+{
+        return 0x004188b0;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
+{
+        return 0x004188b4;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
+{
+        return 0x004188b8;
+}
+static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
+{
+        return 0x004188ac;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+{
+        return 0x00419e10;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+{
+        return 0x1 << 30;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
+{
+        return 0x004041c0;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
+{
+        return 0x00419c84;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
+{
+        return 0x7 << 8;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
+{
+        return 0x100;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
+{
+        return 0x00419f78;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
+{
+        return 0x3 << 11;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
+{
+        return 0x1000;
+}
+static inline u32 gr_gpcs_tc_debug0_r(void)
+{
+        return 0x00418708;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
+{
+        return (v & 0x1ff) << 0;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
+{
+        return 0x1ff << 0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h
new file mode 100644
index 00000000..d760b588
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h
@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gp106_h_
+#define _hw_ltc_gp106_h_
+
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046c;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+        return 0x00140518;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+        return 0x0017e318;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
+{
+        return 0x1 << 15;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+        return 0x00140494;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+        return (r >> 16) & 0x3;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+        return 0x0017e26c;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+        return 0x2;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+        return 0x4;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046c;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+        return 0x0017e270;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+        return (v & 0x3ffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+        return 0x0017e274;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+        return (v & 0x3ffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+        return 0x0003ffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+        return 0x0017e278;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+        return (r >> 0) & 0x3ffffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
+{
+        return 0x0017e27c;
+}
+static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
+{
+        return 0x0017e000;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+        return 0x0017e280;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+        return (r >> 24) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
+{
+        return (r >> 28) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
+{
+        return 0x0017e3f4;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+        return 0x0017e2ac;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+        return (v & 0x1f) << 16;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+        return 0x0017e338;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+        return 0x0017e33c + i*4;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+        return 0x0017e34c;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+        return 32;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+        return 0xffffffff << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+        return 0x0017e2b0;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+        return 0x0017e214;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+        return 0x00140214;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
+{
+        return 0x00142214;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+        return 0x0017e20c;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
+{
+        return 0x200;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+        return 0x1 << 20;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
+{
+        return 0x1 << 30;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
+{
+        return 0x2000000;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+        return 0x0014040c;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
+{
+        return 0x0014051c;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
+{
+        return 0xff << 0;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
+{
+        return 0xff << 16;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
+{
+        return (r >> 16) & 0xff;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x0017e2a0;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+        return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+        return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+        return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x0017e2a4;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+        return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+        return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+        return 0x10000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+        return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001402a0;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001402a4;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001422a0;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001422a4;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
+{
+        return 0x0014058c;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
+{
+        return (r >> 16) & 0x1f;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_mc_gp106.h b/drivers/gpu/nvgpu/gp106/hw_mc_gp106.h
new file mode 100644
index 00000000..99ad8bc0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_mc_gp106.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gp106_h_
+#define _hw_mc_gp106_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+        return 0x00000000;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+        return (r >> 24) & 0x1f;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+        return (r >> 20) & 0xf;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4) & 0xf;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0) & 0xf;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+        return 0x00000100 + i*4;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 mc_intr_replayable_fault_pending_f(void)
+{
+        return 0x200;
+}
+static inline u32 mc_intr_pgraph_pending_f(void)
+{
+        return 0x1000;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 mc_intr_ltc_pending_f(void)
+{
+        return 0x2000000;
+}
+static inline u32 mc_intr_priv_ring_pending_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 mc_intr_pbus_pending_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 mc_intr_en_r(u32 i)
+{
+        return 0x00000140 + i*4;
+}
+static inline u32 mc_intr_en_set_r(u32 i)
+{
+        return 0x00000160 + i*4;
+}
+static inline u32 mc_intr_en_clear_r(u32 i)
+{
+        return 0x00000180 + i*4;
+}
+static inline u32 mc_enable_r(void)
+{
+        return 0x00000200;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+        return 0x4;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+        return 0x8;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+        return 1;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 mc_enable_priv_ring_enabled_f(void)
+{
+        return 0x20;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+        return 0x1 << 6;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+        return 0x100;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+        return 0x1000;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+        return (r >> 13) & 0x1;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+        return 0x2000;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+        return 0x100000;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+        return 0x1 << 21;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+        return 0x200000;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+        return 0x8000000;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 mc_intr_ltc_r(void)
+{
+        return 0x000001c0;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+        return 0x00000204;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+        return 1;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+        return (v & 0x1) << (0 + i*1);
+}
+static inline u32 mc_elpg_enable_r(void)
+{
+        return 0x0000020c;
+}
+static inline u32 mc_elpg_enable_xbar_enabled_f(void)
+{
+        return 0x4;
+}
+static inline u32 mc_elpg_enable_pfb_enabled_f(void)
+{
+        return 0x100000;
+}
+static inline u32 mc_elpg_enable_hub_enabled_f(void)
+{
+        return 0x20000000;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h
new file mode 100644
index 00000000..1e299bae
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pbdma_gp106.h
@@ -0,0 +1,513 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gp106_h_
+#define _hw_pbdma_gp106_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+        return 0x10000004;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+        return (v & 0x1fffff) << 10;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+        return (r >> 10) & 0x1fffff;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+        return 0x00040048 + i*8192;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+        return (v & 0x1fffffff) << 3;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+        return 3;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+        return 0x0004004c + i*8192;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+        return (v & 0x1f) << 16;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+        return 0x00040050 + i*8192;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+        return 0x00040014 + i*8192;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+        return 0x00040000 + i*8192;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+        return 0x00040054 + i*8192;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+        return 0x00040058 + i*8192;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+        return 0x00040018 + i*8192;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+        return 0x0004001c + i*8192;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+        return 0x0004005c + i*8192;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+        return 0x00040060 + i*8192;
+}
+static inline u32 pbdma_formats_r(u32 i)
+{
+        return 0x0004009c + i*8192;
+}
+static inline u32 pbdma_formats_gp_fermi0_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_formats_pb_fermi1_f(void)
+{
+        return 0x100;
+}
+static inline u32 pbdma_formats_mp_fermi0_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+        return 0x00040084 + i*8192;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+        return 0x400000;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+        return 0x60000000;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+        return 0x00040118 + i*8192;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+        return 0x00040094 + i*8192;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+        return 0x000400c0 + i*8192;
+}
+static inline u32 pbdma_method0_fifo_size_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+        return (v & 0xfff) << 2;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+        return (r >> 2) & 0xfff;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+        return (r >> 16) & 0x7;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+        return 0x400000;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+        return 0x000400c8 + i*8192;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+        return 0x000400d0 + i*8192;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+        return 0x000400d8 + i*8192;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+        return 0x000400c4 + i*8192;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+        return 0x000400ac + i*8192;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+        return 0x1f;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+        return 0x00040030 + i*8192;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+        return 0x2;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+        return 0x100;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+        return 0x7800;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+        return 0x7fff8000;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+        return 0x00040100 + i*8192;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+        return 0x00040120 + i*8192;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+        return 0x00040010 + i*8192;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+        return 0xface;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+        return 0x00040008 + i*8192;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+        return 0x2;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+        return 0x3;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+        return (v & 0x7fffff) << 9;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+        return 0x0004000c + i*8192;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 pbdma_config_r(u32 i)
+{
+        return 0x000400f4 + i*8192;
+}
+static inline u32 pbdma_config_auth_level_privileged_f(void)
+{
+        return 0x100;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+        return 0x000400e4 + i*8192;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+        return 0x20;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+        return 0x00040108 + i*8192;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+        return 0x4;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+        return 0x8;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+        return 0x10;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+        return 0x20;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+        return 0x40;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+        return 0x80;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+        return 0x200;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+        return 0x400;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+        return 0x800;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+        return 0x1000;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+        return 0x2000;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+        return 0x4000;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+        return 0x8000;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+        return 0x10000;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+        return 0x20000;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+        return 0x40000;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+        return 0x80000;
+}
+static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
+{
+        return 0x100000;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+        return 0x200000;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+        return 0x400000;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+        return 0x800000;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+        return 0x2000000;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+        return 0x4000000;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+        return 0x8000000;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+        return 0x00040148 + i*8192;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+        return 0x0004010c + i*8192;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+        return 0x100;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+        return 0x0004014c + i*8192;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+        return 0x0004013c + i*8192;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+        return 0x100;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+        return 0x00000008;
+}
+static inline u32 pbdma_runlist_timeslice_r(u32 i)
+{
+        return 0x000400f8 + i*8192;
+}
+static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
+{
+        return 0x80;
+}
+static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
+{
+        return 0x3000;
+}
+static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
+{
+        return 0x10000000;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_perf_gp106.h b/drivers/gpu/nvgpu/gp106/hw_perf_gp106.h
new file mode 100644
index 00000000..cd3501a8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_perf_gp106.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gp106_h_
+#define _hw_perf_gp106_h_
+
+static inline u32 perf_pmasys_control_r(void)
+{
+        return 0x001b4000;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+        return 0x10;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+        return (r >> 5) & 0x1;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+        return 0x20;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+        return 0x001b4070;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+        return (v & 0x3) << 28;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+        return (r >> 28) & 0x3;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+        return 0x0;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+        return 0x001b4074;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+        return (v & 0x7ffffff) << 5;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+        return 0x001b4078;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+        return 0x001b407c;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+        return (v & 0x7ffffff) << 5;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+        return 0x001b4084;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+        return (v & 0xfffffff) << 4;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+        return 0x001b4088;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+        return (v & 0xfffffff) << 4;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+        return 0x001b40a4;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+        return 0x10;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h
new file mode 100644
index 00000000..0eb2187a
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pri_ringmaster_gp106.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gp106_h_
+#define _hw_pri_ringmaster_gp106_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+        return 0x0012004c;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+        return 0x3f << 0;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+        return (r >> 0) & 0x3f;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+        return 0x1;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+        return 0x2;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+        return 0x3;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+        return 0x0;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+        return 0x00120048;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+        return 0x00120050;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+        return 0x00120058;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+        return 0x0012005c;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+        return 0x00120060;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+        return 0x1;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+        return 0x0;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+        return 0x00120074;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+        return 0x00120078;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 pri_ringmaster_enum_ltc_r(void)
+{
+        return 0x0012006c;
+}
+static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h
new file mode 100644
index 00000000..a22d6a05
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pri_ringstation_sys_gp106.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gp106_h_
+#define _hw_pri_ringstation_sys_gp106_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+        return 0x00122300 + i*4;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+        return 0x00122204;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+        return 0x7 << 0;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+        return 0x1;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h b/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
new file mode 100644
index 00000000..8042bcae
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gp106_h_
+#define _hw_proj_gp106_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+        return 0x00500000;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+        return 0x00418000;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+        return 0x00008000;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+        return 0x00002000;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+        return 0x00000200;
+}
+static inline u32 proj_fbpa_base_v(void)
+{
+        return 0x00900000;
+}
+static inline u32 proj_fbpa_shared_base_v(void)
+{
+        return 0x009a0000;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+        return 0x00004000;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+        return 0x00003000;
+}
+static inline u32 proj_ppc_in_gpc_shared_base_v(void)
+{
+        return 0x00003e00;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+        return 0x00000200;
+}
+static inline u32 proj_rop_base_v(void)
+{
+        return 0x00410000;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+        return 0x00408800;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+        return 0x00000400;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+        return 0x00004000;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+        return 0x00000800;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+        return 0x00001800;
+}
+static inline u32 proj_host_num_engines_v(void)
+{
+        return 0x00000009;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+        return 0x00000005;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+        return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+        return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+        return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+        return 0x00000020;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+        return 0x00000008;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_psec_gp106.h b/drivers/gpu/nvgpu/gp106/hw_psec_gp106.h
new file mode 100644
index 00000000..f9c9f69c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_psec_gp106.h
@@ -0,0 +1,609 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_psec_gp106_h_
+#define _hw_psec_gp106_h_
+
+static inline u32 psec_falcon_irqsset_r(void)
+{
+        return 0x00087000;
+}
+static inline u32 psec_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40;
+}
+static inline u32 psec_falcon_irqsclr_r(void)
+{
+        return 0x00087004;
+}
+static inline u32 psec_falcon_irqstat_r(void)
+{
+        return 0x00087008;
+}
+static inline u32 psec_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10;
+}
+static inline u32 psec_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20;
+}
+static inline u32 psec_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40;
+}
+static inline u32 psec_falcon_irqmode_r(void)
+{
+        return 0x0008700c;
+}
+static inline u32 psec_falcon_irqmset_r(void)
+{
+        return 0x00087010;
+}
+static inline u32 psec_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 psec_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 7;
+}
+static inline u32 psec_falcon_irqmclr_r(void)
+{
+        return 0x00087014;
+}
+static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 psec_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 7;
+}
+static inline u32 psec_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_irqmask_r(void)
+{
+        return 0x00087018;
+}
+static inline u32 psec_falcon_irqdest_r(void)
+{
+        return 0x0008701c;
+}
+static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 psec_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 7;
+}
+static inline u32 psec_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 16;
+}
+static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 17;
+}
+static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1) << 18;
+}
+static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 19;
+}
+static inline u32 psec_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1) << 20;
+}
+static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1) << 21;
+}
+static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 22;
+}
+static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 23;
+}
+static inline u32 psec_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xff) << 24;
+}
+static inline u32 psec_falcon_curctx_r(void)
+{
+        return 0x00087050;
+}
+static inline u32 psec_falcon_nxtctx_r(void)
+{
+        return 0x00087054;
+}
+static inline u32 psec_falcon_mailbox0_r(void)
+{
+        return 0x00087040;
+}
+static inline u32 psec_falcon_mailbox1_r(void)
+{
+        return 0x00087044;
+}
+static inline u32 psec_falcon_itfen_r(void)
+{
+        return 0x00087048;
+}
+static inline u32 psec_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1;
+}
+static inline u32 psec_falcon_idlestate_r(void)
+{
+        return 0x0008704c;
+}
+static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1) & 0x7fff;
+}
+static inline u32 psec_falcon_os_r(void)
+{
+        return 0x00087080;
+}
+static inline u32 psec_falcon_engctl_r(void)
+{
+        return 0x000870a4;
+}
+static inline u32 psec_falcon_cpuctl_r(void)
+{
+        return 0x00087100;
+}
+static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1 << 6;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6) & 0x1;
+}
+static inline u32 psec_falcon_cpuctl_alias_r(void)
+{
+        return 0x00087130;
+}
+static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 psec_falcon_imemc_r(u32 i)
+{
+        return 0x00087180 + i*16;
+}
+static inline u32 psec_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 psec_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 psec_falcon_imemd_r(u32 i)
+{
+        return 0x00087184 + i*16;
+}
+static inline u32 psec_falcon_imemt_r(u32 i)
+{
+        return 0x00087188 + i*16;
+}
+static inline u32 psec_falcon_sctl_r(void)
+{
+        return 0x00087240;
+}
+static inline u32 psec_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4;
+}
+static inline u32 psec_falcon_bootvec_r(void)
+{
+        return 0x00087104;
+}
+static inline u32 psec_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 psec_falcon_dmactl_r(void)
+{
+        return 0x0008710c;
+}
+static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 psec_falcon_hwcfg_r(void)
+{
+        return 0x00087108;
+}
+static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0) & 0x1ff;
+}
+static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9) & 0x1ff;
+}
+static inline u32 psec_falcon_dmatrfbase_r(void)
+{
+        return 0x00087110;
+}
+static inline u32 psec_falcon_dmatrfbase1_r(void)
+{
+        return 0x00087128;
+}
+static inline u32 psec_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00087114;
+}
+static inline u32 psec_falcon_dmatrfcmd_r(void)
+{
+        return 0x00087118;
+}
+static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 psec_falcon_dmatrffboffs_r(void)
+{
+        return 0x0008711c;
+}
+static inline u32 psec_falcon_exterraddr_r(void)
+{
+        return 0x00087168;
+}
+static inline u32 psec_falcon_exterrstat_r(void)
+{
+        return 0x0008716c;
+}
+static inline u32 psec_falcon_exterrstat_valid_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 psec_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 psec_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_r(void)
+{
+        return 0x00087200;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void)
+{
+        return 4;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void)
+{
+        return 0xf << 0;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0) & 0xf;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xe;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1f) << 8;
+}
+static inline u32 psec_sec2_falcon_icd_rdata_r(void)
+{
+        return 0x0008720c;
+}
+static inline u32 psec_falcon_dmemc_r(u32 i)
+{
+        return 0x000871c0 + i*8;
+}
+static inline u32 psec_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 psec_falcon_dmemc_offs_m(void)
+{
+        return 0x3f << 2;
+}
+static inline u32 psec_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 psec_falcon_dmemc_blk_m(void)
+{
+        return 0xff << 8;
+}
+static inline u32 psec_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 psec_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1) << 25;
+}
+static inline u32 psec_falcon_dmemd_r(u32 i)
+{
+        return 0x000871c4 + i*8;
+}
+static inline u32 psec_falcon_debug1_r(void)
+{
+        return 0x00087090;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1) << 16;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1 << 16;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 psec_fbif_transcfg_r(u32 i)
+{
+        return 0x00087600 + i*4;
+}
+static inline u32 psec_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0;
+}
+static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1;
+}
+static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2;
+}
+static inline u32 psec_fbif_transcfg_mem_type_s(void)
+{
+        return 1;
+}
+static inline u32 psec_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 psec_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 psec_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0;
+}
+static inline u32 psec_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4;
+}
+static inline u32 psec_falcon_engine_r(void)
+{
+        return 0x000873c0;
+}
+static inline u32 psec_falcon_engine_reset_true_f(void)
+{
+        return 0x1;
+}
+static inline u32 psec_falcon_engine_reset_false_f(void)
+{
+        return 0x0;
+}
+static inline u32 psec_fbif_ctl_r(void)
+{
+        return 0x00087624;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void)
+{
+        return 0x0;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void)
+{
+        return 0x80;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h
new file mode 100644
index 00000000..b4dfea0d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_pwr_gp106.h
@@ -0,0 +1,841 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gp106_h_
+#define _hw_pwr_gp106_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+        return 0x0010a000;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+        return 0x0010a004;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+        return 0x0010a008;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+        return 0x0010a00c;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+        return 0x0010a010;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+        return 0x0010a014;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+        return 0x0010a018;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+        return 0x0010a01c;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1) << 16;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1) << 17;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1) << 18;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1) << 19;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1) << 20;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1) << 21;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1) << 22;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1) << 23;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xff) << 24;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+        return 0x0010a050;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+        return 0x0010a054;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+        return 0x0010a040;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+        return 0x0010a044;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+        return 0x0010a048;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+        return 0x0010a04c;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1) & 0x7fff;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+        return 0x0010a080;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+        return 0x0010a0a4;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+        return 0x0010a100;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1 << 6;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6) & 0x1;
+}
+static inline u32 pwr_falcon_cpuctl_alias_r(void)
+{
+        return 0x0010a130;
+}
+static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 pwr_pmu_scpctl_stat_r(void)
+{
+        return 0x0010ac08;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
+{
+        return (v & 0x1) << 20;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
+{
+        return 0x1 << 20;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
+{
+        return (r >> 20) & 0x1;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+        return 0x0010a180 + i*16;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+        return 0x0010a184 + i*16;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+        return 0x0010a188 + i*16;
+}
+static inline u32 pwr_falcon_sctl_r(void)
+{
+        return 0x0010a240;
+}
+static inline u32 pwr_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+        return 0x0010a104;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+        return 0x0010a10c;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+        return 0x0010a108;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0) & 0x1ff;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9) & 0x1ff;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+        return 0x0010a110;
+}
+static inline u32 pwr_falcon_dmatrfbase1_r(void)
+{
+        return 0x0010a128;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+        return 0x0010a114;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+        return 0x0010a118;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7) << 8;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7) << 12;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+        return 0x0010a11c;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+        return 0x0010a168;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+        return 0x0010a16c;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+        return 0x0010a200;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+        return 4;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+        return 0xf << 0;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0) & 0xf;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xe;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1f) << 8;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+        return 0x0010a20c;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+        return 0x0010a1c0 + i*8;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+        return 0x3f << 2;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+        return 0xff << 8;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1) << 25;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+        return 0x0010a1c4 + i*8;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+        return 0x0010a480;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+        return (v & 0xfffffff) << 0;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+        return 0x0;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+        return 0x30000000;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+        return (v & 0x1) << 30;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+        return 0x0010a488;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+        return 0x000000ff;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+        return 0x0010a48c;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+        return 0xff << 0;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+        return 0x0010a580 + i*4;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+        return (r >> 0) & 0xff;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+        return 0x0;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+        return 0x0010a4a0 + i*4;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+        return 0x0010a4b0 + i*4;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+        return 0x0010a4c8;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+        return 0x0010a4cc;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+        return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+        return 0x0010a504 + i*16;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+        return 0x1;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+        return 0x200000;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+        return 0x0010a508 + i*16;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+        return (v & 0x7fffffff) << 0;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+        return (r >> 0) & 0x7fffffff;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+        return 0x0010a50c + i*16;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+        return 0x2;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+        return 0x3;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+        return 0x0010a9f0 + i*8;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+        return 0x0010a9f4 + i*8;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+        return 0x0010aa30 + i*8;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+        return 0x0010a5c0 + i*4;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+        return 0x0010a450 + i*4;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+        return 0x0010a7a0;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+        return 0x0010a7a4;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+        return 0x0010a7ac;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+        return 0x0010a7a8;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+        return 0x0010a988;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+        return 0x0010a7b0;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+        return 0x0010a6c0 + i*4;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+        return 0x0010a6e8 + i*4;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+        return 0x0010a710 + i*4;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+        return 0x0010a760 + i*4;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+        return 0x0010ae00 + i*4;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+        return 1;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4;
+}
+static inline u32 pwr_falcon_engine_r(void)
+{
+        return 0x0010a3c0;
+}
+static inline u32 pwr_falcon_engine_reset_true_f(void)
+{
+        return 0x1;
+}
+static inline u32 pwr_falcon_engine_reset_false_f(void)
+{
+        return 0x0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_ram_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ram_gp106.h
new file mode 100644
index 00000000..eb02ac28
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_ram_gp106.h
@@ -0,0 +1,481 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gp106_h_
+#define _hw_ram_gp106_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+        return 4096;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+        return 0;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+        return 128;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+        return 0x0;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+        return 0x2;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x3;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+        return 128;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+        return 0x4;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
+{
+        return 128;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
+{
+        return 0x10;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
+{
+        return 0x1 << 5;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
+{
+        return 128;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
+{
+        return 0x20;
+}
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+        return (v & 0x1) << 11;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+        return 0x1 << 11;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+        return 128;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+        return 0x0;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+        return 0x800;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+        return 128;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+        return 129;
+}
+static inline u32 ram_in_adr_limit_lo_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_adr_limit_lo_w(void)
+{
+        return 130;
+}
+static inline u32 ram_in_adr_limit_hi_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 ram_in_adr_limit_hi_w(void)
+{
+        return 131;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+        return 132;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+        return 0x0;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+        return 0x8;
+}
+static inline u32 ram_in_gr_cs_w(void)
+{
+        return 132;
+}
+static inline u32 ram_in_gr_cs_wfi_f(void)
+{
+        return 0x0;
+}
+static inline u32 ram_in_gr_wfi_target_w(void)
+{
+        return 132;
+}
+static inline u32 ram_in_gr_wfi_mode_w(void)
+{
+        return 132;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_f(void)
+{
+        return 0x0;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
+{
+        return 0x4;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
+{
+        return 132;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
+{
+        return 133;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+        return 0x00001000;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+        return 0x00000200;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+        return 0;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+        return 2;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+        return 3;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+        return 4;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+        return 5;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+        return 6;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+        return 7;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+        return 8;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+        return 9;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+        return 12;
+}
+static inline u32 ram_fc_semaphorea_w(void)
+{
+        return 14;
+}
+static inline u32 ram_fc_semaphoreb_w(void)
+{
+        return 15;
+}
+static inline u32 ram_fc_semaphorec_w(void)
+{
+        return 16;
+}
+static inline u32 ram_fc_semaphored_w(void)
+{
+        return 17;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+        return 18;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+        return 19;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+        return 20;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+        return 21;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+        return 22;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+        return 23;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+        return 24;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+        return 33;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+        return 34;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+        return 37;
+}
+static inline u32 ram_fc_formats_w(void)
+{
+        return 39;
+}
+static inline u32 ram_fc_target_w(void)
+{
+        return 43;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+        return 57;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+        return 58;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+        return 0;
+}
+static inline u32 ram_fc_config_w(void)
+{
+        return 61;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+        return 62;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+        return 0x00000009;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+        return 0x00000200;
+}
+static inline u32 ram_userd_put_w(void)
+{
+        return 16;
+}
+static inline u32 ram_userd_get_w(void)
+{
+        return 17;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+        return 18;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+        return 19;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+        return 20;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+        return 22;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+        return 23;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+        return 24;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+        return 34;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+        return 35;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+        return 22;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+        return 23;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+        return (v & 0x1) << 13;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+        return 0x0;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+        return 0x2000;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+        return (v & 0xf) << 14;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+        return 0xc000;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xff) << 18;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+        return 0x2000000;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+        return (v & 0x3f) << 26;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_therm_gp106.h b/drivers/gpu/nvgpu/gp106/hw_therm_gp106.h
new file mode 100644
index 00000000..36ffcc7a
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_therm_gp106.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_therm_gp106_h_
+#define _hw_therm_gp106_h_
+
+static inline u32 therm_temp_sensor_tsense_r(void)
+{
+        return 0x00020460;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_f(u32 v)
+{
+        return (v & 0x3fff) << 3;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_m(void)
+{
+        return 0x3fff << 3;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_v(u32 r)
+{
+        return (r >> 3) & 0x3fff;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_min_v(void)
+{
+        return 0x00003b00;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_max_v(void)
+{
+        return 0x000010e0;
+}
+static inline u32 therm_temp_sensor_tsense_state_f(u32 v)
+{
+        return (v & 0x3) << 29;
+}
+static inline u32 therm_temp_sensor_tsense_state_m(void)
+{
+        return 0x3 << 29;
+}
+static inline u32 therm_temp_sensor_tsense_state_v(u32 r)
+{
+        return (r >> 29) & 0x3;
+}
+static inline u32 therm_temp_sensor_tsense_state_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 therm_temp_sensor_tsense_state_shadow_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+        return 0x00020200 + i*4;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+        return 0x0;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+        return 0x1;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+        return 0x2;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+        return 0x3 << 2;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+        return 0x0;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+        return 0x4;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+        return (v & 0x1f) << 8;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+        return 0x1f << 8;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+        return (v & 0x7) << 13;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+        return 0x7 << 13;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+        return (v & 0xf) << 16;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+        return 0xf << 16;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+        return (v & 0xf) << 20;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+        return 0xf << 20;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+        return 0x00020288;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+        return 0xffffffff << 0;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+        return 0x0002028c;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+        return 0xffffffff << 0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_timer_gp106.h b/drivers/gpu/nvgpu/gp106/hw_timer_gp106.h
new file mode 100644
index 00000000..62771628
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_timer_gp106.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gp106_h_
+#define _hw_timer_gp106_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+        return 0x00009080;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+        return (v & 0xffffff) << 0;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+        return 0xffffff << 0;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+        return (r >> 0) & 0xffffff;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+        return 0x00009084;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+        return 0x00009088;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+        return 0x0000908c;
+}
+static inline u32 timer_time_0_r(void)
+{
+        return 0x00009400;
+}
+static inline u32 timer_time_1_r(void)
+{
+        return 0x00009410;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_top_gp106.h b/drivers/gpu/nvgpu/gp106/hw_top_gp106.h
new file mode 100644
index 00000000..85350954
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_top_gp106.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gp106_h_
+#define _hw_top_gp106_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+        return 0x00022430;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+        return 0x00022434;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_fbps_r(void)
+{
+        return 0x00022438;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_fbpas_r(void)
+{
+        return 0x0002243c;
+}
+static inline u32 top_num_fbpas_value_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 top_ltc_per_fbp_r(void)
+{
+        return 0x00022450;
+}
+static inline u32 top_ltc_per_fbp_value_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 top_slices_per_ltc_r(void)
+{
+        return 0x0002245c;
+}
+static inline u32 top_slices_per_ltc_value_v(u32 r)
+{
+        return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_ltcs_r(void)
+{
+        return 0x00022454;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+        return 0x00022700 + i*4;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+        return 0x00000040;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+        return (r >> 26) & 0xf;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+        return (r >> 21) & 0xf;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+        return (r >> 15) & 0x1f;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+        return (r >> 9) & 0x1f;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+        return (r >> 2) & 0x1fffffff;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+        return 0x0;
+}
+static inline u32 top_device_info_type_enum_copy0_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 top_device_info_type_enum_copy0_f(void)
+{
+        return 0x4;
+}
+static inline u32 top_device_info_type_enum_lce_v(void)
+{
+        return 0x00000013;
+}
+static inline u32 top_device_info_type_enum_lce_f(void)
+{
+        return 0x4c;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 top_device_info_entry_data_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 top_device_info_data_inst_id_v(u32 r)
+{
+        return (r >> 26) & 0xf;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+        return (r >> 12) & 0xfff;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+        return (r >> 3) & 0x1f;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 top_scratch1_r(void)
+{
+        return 0x0002240c;
+}
+static inline u32 top_scratch1_devinit_completed_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_trim_gp106.h b/drivers/gpu/nvgpu/gp106/hw_trim_gp106.h
new file mode 100644
index 00000000..42d3fd32
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_trim_gp106.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_trim_gp106_h_
+#define _hw_trim_gp106_h_
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void)
+{
+        return 0x00132924;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s(void)
+{
+        return 16;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m(void)
+{
+        return 0xffff << 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s(void)
+{
+        return 1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(u32 v)
+{
+        return (v & 0x1) << 16;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m(void)
+{
+        return 0x1 << 16;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void)
+{
+        return 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
+{
+        return 0x10000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s(void)
+{
+        return 1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(u32 v)
+{
+        return (v & 0x1) << 20;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m(void)
+{
+        return 0x1 << 20;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r)
+{
+        return (r >> 20) & 0x1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void)
+{
+        return 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
+{
+        return 0x100000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s(void)
+{
+        return 1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m(void)
+{
+        return 0x1 << 24;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r)
+{
+        return (r >> 24) & 0x1;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void)
+{
+        return 0;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(void)
+{
+        return 0x70000000;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(void)
+{
+        return 0x00132928;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void)
+{
+        return 0x00132128;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void)
+{
+        return 0x0013212c;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_r(void)
+{
+        return 0x001373c0;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cnt_r(void)
+{
+        return 0x001373c4;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_r(void)
+{
+        return 0x001373b0;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(void)
+{
+        return 0x0;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void)
+{
+        return 0x001373b4;
+}
+
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_xp_gp106.h b/drivers/gpu/nvgpu/gp106/hw_xp_gp106.h
new file mode 100644
index 00000000..40b14da1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_xp_gp106.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xp_gp106_h_
+#define _hw_xp_gp106_h_
+
+static inline u32 xp_dl_mgr_r(u32 i)
+{
+        return 0x0008b8c0 + i*4;
+}
+static inline u32 xp_dl_mgr_safe_timing_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 xp_pl_link_config_r(u32 i)
+{
+        return 0x0008c040 + i*4;
+}
+static inline u32 xp_pl_link_config_ltssm_status_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 xp_pl_link_config_ltssm_status_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
+{
+        return (v & 0xf) << 0;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_m(void)
+{
+        return 0xf << 0;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
+{
+        return (v & 0x3) << 18;
+}
+static inline u32 xp_pl_link_config_max_link_rate_m(void)
+{
+        return 0x3 << 18;
+}
+static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 xp_pl_link_config_target_tx_width_m(void)
+{
+        return 0x7 << 20;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
+{
+        return 0x00000007;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x2_v(void)
+{
+        return 0x00000006;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x4_v(void)
+{
+        return 0x00000005;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x8_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x16_v(void)
+{
+        return 0x00000000;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/hw_xve_gp106.h b/drivers/gpu/nvgpu/gp106/hw_xve_gp106.h
new file mode 100644
index 00000000..24434ae0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hw_xve_gp106.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xve_gp106_h_
+#define _hw_xve_gp106_h_
+
+static inline u32 xve_rom_ctrl_r(void)
+{
+        return 0x00000050;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
+{
+        return 0x1;
+}
+static inline u32 xve_link_control_status_r(void)
+{
+        return 0x00000088;
+}
+static inline u32 xve_link_control_status_link_speed_m(void)
+{
+        return 0xf << 16;
+}
+static inline u32 xve_link_control_status_link_speed_v(u32 r)
+{
+        return (r >> 16) & 0xf;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 xve_link_control_status_link_width_m(void)
+{
+        return 0x3f << 20;
+}
+static inline u32 xve_link_control_status_link_width_v(u32 r)
+{
+        return (r >> 20) & 0x3f;
+}
+static inline u32 xve_link_control_status_link_width_x1_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 xve_link_control_status_link_width_x2_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 xve_link_control_status_link_width_x4_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 xve_link_control_status_link_width_x8_v(void)
+{
+        return 0x00000008;
+}
+static inline u32 xve_link_control_status_link_width_x16_v(void)
+{
+        return 0x00000010;
+}
+static inline u32 xve_priv_xv_r(void)
+{
+        return 0x00000150;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
+{
+        return (v & 0x1) << 7;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
+{
+        return 0x1 << 7;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
+{
+        return (r >> 7) & 0x1;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_m(void)
+{
+        return 0x1 << 8;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
+{
+        return (r >> 8) & 0x1;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/ltc_gp106.c b/drivers/gpu/nvgpu/gp106/ltc_gp106.c
new file mode 100644
index 00000000..b162ddb3
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/ltc_gp106.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+#include "gm20b/ltc_gm20b.h"
+#include "gp10b/ltc_gp10b.h"
+#include "gp106/ltc_gp106.h"
+
+void gp106_init_ltc(struct gpu_ops *gops)
+{
+        gp10b_init_ltc(gops);
+
+        /* dGPU does not need the LTC hack */
+        gops->ltc.cbc_fix_config = NULL;
+        gops->ltc.init_cbc = NULL;
+        gops->ltc.init_fs_state = gm20b_ltc_init_fs_state;
+}
diff --git a/drivers/gpu/nvgpu/gp106/ltc_gp106.h b/drivers/gpu/nvgpu/gp106/ltc_gp106.h
new file mode 100644
index 00000000..4720d7a1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/ltc_gp106.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef LTC_GP106_H
+#define LTC_GP106_H
+struct gpu_ops;
+
+void gp106_init_ltc(struct gpu_ops *gops);
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/mm_gp106.c b/drivers/gpu/nvgpu/gp106/mm_gp106.c
new file mode 100644
index 00000000..3309a0d7
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/mm_gp106.c
@@ -0,0 +1,41 @@
+/*
+ * GP106 memory management
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gp10b/mm_gp10b.h"
+#include "gp106/mm_gp106.h"
+
+#include "hw_fb_gp106.h"
+
+static size_t gp106_mm_get_vidmem_size(struct gk20a *g)
+{
+        u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r());
+        u32 mag = fb_mmu_local_memory_range_lower_mag_v(range);
+        u32 scale = fb_mmu_local_memory_range_lower_scale_v(range);
+        u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range);
+        size_t bytes = ((size_t)mag << scale) * SZ_1M;
+
+        if (ecc)
+                bytes = bytes / 16 * 15;
+
+        return bytes;
+}
+
+void gp106_init_mm(struct gpu_ops *gops)
+{
+        gp10b_init_mm(gops);
+        gops->mm.get_vidmem_size = gp106_mm_get_vidmem_size;
+        gops->mm.get_physical_addr_bits = NULL;
+}
diff --git a/drivers/gpu/nvgpu/gp106/mm_gp106.h b/drivers/gpu/nvgpu/gp106/mm_gp106.h
new file mode 100644
index 00000000..36a89a11
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/mm_gp106.h
@@ -0,0 +1,23 @@
+/*
+ * GP106 memory management
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef MM_GP106_H
+#define MM_GP106_H
+
+struct gpu_ops;
+
+void gp106_init_mm(struct gpu_ops *gops);
+
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
new file mode 100644
index 00000000..eecd7351
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>        /* for udelay */
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+
+#include "gm206/pmu_gm206.h"
+#include "gm20b/pmu_gm20b.h"
+#include "gp10b/pmu_gp10b.h"
+#include "gp106/pmu_gp106.h"
+#include "gp106/acr_gp106.h"
+#include "gp106/hw_psec_gp106.h"
+#include "clk/clk_mclk.h"
+#include "hw_mc_gp106.h"
+#include "hw_pwr_gp106.h"
+#include "lpwr/lpwr.h"
+#include "lpwr/rppg.h"
+
+#define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000
+#define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
+
+static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
+{
+        struct gk20a *g = gk20a_from_pmu(pmu);
+
+        gk20a_dbg_fn("");
+
+        /*
+        * From GP10X onwards, we are using PPWR_FALCON_ENGINE for reset. And as
+        * it may come into same behaviour, reading NV_PPWR_FALCON_ENGINE again
+        * after Reset.
+        */
+
+        if (enable) {
+                int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX /
+                                PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT;
+                gk20a_writel(g, pwr_falcon_engine_r(),
+                        pwr_falcon_engine_reset_false_f());
+                gk20a_readl(g, pwr_falcon_engine_r());
+
+                /* make sure ELPG is in a good state */
+                if (g->ops.clock_gating.slcg_pmu_load_gating_prod)
+                        g->ops.clock_gating.slcg_pmu_load_gating_prod(g,
+                                        g->slcg_enabled);
+                if (g->ops.clock_gating.blcg_pmu_load_gating_prod)
+                        g->ops.clock_gating.blcg_pmu_load_gating_prod(g,
+                                        g->blcg_enabled);
+
+                /* wait for Scrubbing to complete */
+                do {
+                        u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) &
+                                (pwr_falcon_dmactl_dmem_scrubbing_m() |
+                                 pwr_falcon_dmactl_imem_scrubbing_m());
+
+                        if (!w) {
+                                gk20a_dbg_fn("done");
+                                return 0;
+                        }
+                        udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT);
+                } while (--retries || !tegra_platform_is_silicon());
+
+                /* If scrubbing timeout, keep PMU in reset state */
+                gk20a_writel(g, pwr_falcon_engine_r(),
+                        pwr_falcon_engine_reset_true_f());
+                gk20a_readl(g, pwr_falcon_engine_r());
+                gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout");
+                return -ETIMEDOUT;
+        } else {
+                /* DISBALE */
+                gk20a_writel(g, pwr_falcon_engine_r(),
+                        pwr_falcon_engine_reset_true_f());
+                gk20a_readl(g, pwr_falcon_engine_r());
+                return 0;
+        }
+}
+
+static int pmu_enable(struct pmu_gk20a *pmu, bool enable)
+{
+        struct gk20a *g = gk20a_from_pmu(pmu);
+        u32 reg_reset;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        if (!enable) {
+                reg_reset = gk20a_readl(g, pwr_falcon_engine_r());
+                if (reg_reset !=
+                        pwr_falcon_engine_reset_true_f()) {
+
+                        pmu_enable_irq(pmu, false);
+                        gp106_pmu_enable_hw(pmu, false);
+                        udelay(10);
+                }
+        } else {
+                gp106_pmu_enable_hw(pmu, true);
+                /* TBD: post reset */
+
+                /*idle the PMU and enable interrupts on the Falcon*/
+                err = pmu_idle(pmu);
+                if (err)
+                        return err;
+                udelay(5);
+                pmu_enable_irq(pmu, true);
+        }
+
+        gk20a_dbg_fn("done");
+        return 0;
+}
+
+static int gp106_pmu_reset(struct gk20a *g)
+{
+        struct pmu_gk20a *pmu = &g->pmu;
+        int err = 0;
+
+        gk20a_dbg_fn("");
+
+        err = pmu_idle(pmu);
+        if (err)
+                return err;
+
+        /* TBD: release pmu hw mutex */
+
+        err = pmu_enable(pmu, false);
+        if (err)
+                return err;
+
+        /* TBD: cancel all sequences */
+        /* TBD: init all sequences and state tables */
+        /* TBD: restore pre-init message handler */
+
+        err = pmu_enable(pmu, true);
+        if (err)
+                return err;
+
+        return err;
+}
+
+static int gp106_sec2_reset(struct gk20a *g)
+{
+        gk20a_dbg_fn("");
+        //sec2 reset
+        gk20a_writel(g, psec_falcon_engine_r(),
+                        pwr_falcon_engine_reset_true_f());
+        udelay(10);
+        gk20a_writel(g, psec_falcon_engine_r(),
+                        pwr_falcon_engine_reset_false_f());
+
+        gk20a_dbg_fn("done");
+        return 0;
+}
+
+static int gp106_falcon_reset(struct gk20a *g)
+{
+        gk20a_dbg_fn("");
+
+        gp106_pmu_reset(g);
+        gp106_sec2_reset(g);
+
+        gk20a_dbg_fn("done");
+        return 0;
+}
+
+static bool gp106_is_pmu_supported(struct gk20a *g)
+{
+        return true;
+}
+
+static u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id)
+{
+        if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS)
+                return PMU_PG_FEATURE_GR_RPPG_ENABLED;
+
+        if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS)
+                return NVGPU_PMU_MS_FEATURE_MASK_ALL;
+
+        return 0;
+}
+
+static u32 gp106_pmu_pg_engines_list(struct gk20a *g)
+{
+        return BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
+                        BIT(PMU_PG_ELPG_ENGINE_ID_MS);
+}
+
+static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg,
+                        void *param, u32 handle, u32 status)
+{
+        gk20a_dbg_fn("");
+
+        if (status != 0) {
+                gk20a_err(dev_from_gk20a(g), "PG PARAM cmd aborted");
+                return;
+        }
+
+        gp106_dbg_pmu("PG PARAM is acknowledged from PMU %x",
+                        msg->msg.pg.msg_type);
+}
+
+static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
+{
+        struct pmu_gk20a *pmu = &g->pmu;
+        struct pmu_cmd cmd;
+        u32 seq;
+        u32 status;
+
+        memset(&cmd, 0, sizeof(struct pmu_cmd));
+        if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) {
+
+                status = init_rppg(g);
+                if (status != 0) {
+                        gk20a_err(dev_from_gk20a(g), "RPPG init Failed");
+                        return -1;
+                }
+
+                cmd.hdr.unit_id = PMU_UNIT_PG;
+                cmd.hdr.size = PMU_CMD_HDR_SIZE +
+                                sizeof(struct pmu_pg_cmd_gr_init_param);
+                cmd.cmd.pg.gr_init_param.cmd_type =
+                                PMU_PG_CMD_ID_PG_PARAM;
+                cmd.cmd.pg.gr_init_param.sub_cmd_id =
+                                PMU_PG_PARAM_CMD_GR_INIT_PARAM;
+                cmd.cmd.pg.gr_init_param.featuremask =
+                                PMU_PG_FEATURE_GR_RPPG_ENABLED;
+
+                gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM");
+                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                                pmu_handle_param_msg, pmu, &seq, ~0);
+        } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) {
+                cmd.hdr.unit_id = PMU_UNIT_PG;
+                cmd.hdr.size = PMU_CMD_HDR_SIZE +
+                        sizeof(struct pmu_pg_cmd_ms_init_param);
+                cmd.cmd.pg.ms_init_param.cmd_type =
+                        PMU_PG_CMD_ID_PG_PARAM;
+                cmd.cmd.pg.ms_init_param.cmd_id =
+                        PMU_PG_PARAM_CMD_MS_INIT_PARAM;
+                cmd.cmd.pg.ms_init_param.support_mask =
+                        NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |
+                        NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |
+                        NVGPU_PMU_MS_FEATURE_MASK_RPPG |
+                        NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING;
+
+                gp106_dbg_pmu("cmd post MS PMU_PG_CMD_ID_PG_PARAM");
+                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                        pmu_handle_param_msg, pmu, &seq, ~0);
+        }
+
+        return 0;
+}
+
+void gp106_init_pmu_ops(struct gpu_ops *gops)
+{
+        gk20a_dbg_fn("");
+
+        if (gops->privsecurity) {
+                gp106_init_secure_pmu(gops);
+                gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
+                gops->pmu.load_lsfalcon_ucode = gm206_load_falcon_ucode;
+                gops->pmu.is_lazy_bootstrap = gm206_is_lazy_bootstrap;
+                gops->pmu.is_priv_load = gm206_is_priv_load;
+        } else {
+                gk20a_init_pmu_ops(gops);
+                gops->pmu.pmu_setup_hw_and_bootstrap =
+                        gm20b_init_nspmu_setup_hw1;
+                gops->pmu.load_lsfalcon_ucode = NULL;
+                gops->pmu.init_wpr_region = NULL;
+        }
+        gops->pmu.pmu_setup_elpg = NULL;
+        gops->pmu.lspmuwprinitdone = 0;
+        gops->pmu.fecsbootstrapdone = false;
+        gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
+        gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics;
+        gops->pmu.pmu_pg_init_param = gp106_pg_param_init;
+        gops->pmu.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list;
+        gops->pmu.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list;
+        gops->pmu.pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg;
+        gops->pmu.pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg;
+        gops->pmu.pmu_pg_param_post_init = nvgpu_lpwr_post_init;
+        gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
+        gops->pmu.dump_secure_fuses = NULL;
+        gops->pmu.reset = gp106_falcon_reset;
+        gops->pmu.mclk_init = clk_mclkseq_init_mclk_gddr5;
+        gops->pmu.is_pmu_supported = gp106_is_pmu_supported;
+
+        gk20a_dbg_fn("done");
+}
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
new file mode 100644
index 00000000..a42ff620
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __PMU_GP106_H_
+#define __PMU_GP106_H_
+
+#define gp106_dbg_pmu(fmt, arg...) \
+        gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
+
+void gp106_init_pmu_ops(struct gpu_ops *gops);
+
+#endif /*__PMU_GP106_H_*/
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c
new file mode 100644
index 00000000..5b6897c1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.c
@@ -0,0 +1,1815 @@
+/*
+ * Tegra GP106 GPU Debugger Driver Register Ops
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/bsearch.h>
+#include <uapi/linux/nvgpu.h>
+
+#include "gk20a/gk20a.h"
+#include "gk20a/dbg_gpu_gk20a.h"
+#include "gk20a/regops_gk20a.h"
+#include "regops_gp106.h"
+
+static const struct regop_offset_range gp106_global_whitelist_ranges[] = {
+        { 0x000004f0,   1},
+        { 0x00001a00,   3},
+        { 0x00002800, 128},
+        { 0x00009400,   1},
+        { 0x00009410,   1},
+        { 0x00009480,   1},
+        { 0x00020200,  24},
+        { 0x00021c04,   3},
+        { 0x00021c14,   3},
+        { 0x00021c24,  71},
+        { 0x00021d44,   1},
+        { 0x00021d4c,   1},
+        { 0x00021d54,   1},
+        { 0x00021d5c,   1},
+        { 0x00021d68,  19},
+        { 0x00021dbc,  16},
+        { 0x00022430,   7},
+        { 0x00022450,   1},
+        { 0x0002245c,   2},
+        { 0x00070000,   5},
+        { 0x000840a8,   1},
+        { 0x00084b5c,   1},
+        { 0x000870a8,   1},
+        { 0x000884e0,   1},
+        { 0x000884f4,   1},
+        { 0x0008e00c,   1},
+        { 0x00100c18,   3},
+        { 0x00100c84,   1},
+        { 0x0010a0a8,   1},
+        { 0x0010a4f0,   1},
+        { 0x0013c808,   2},
+        { 0x0013cc14,   1},
+        { 0x0013cc34,   1},
+        { 0x0013cc54,   1},
+        { 0x0013cc74,   1},
+        { 0x0013cc94,   1},
+        { 0x0013ccb4,   1},
+        { 0x0013ec18,   1},
+        { 0x00140028,   1},
+        { 0x00140280,   1},
+        { 0x001402a0,   1},
+        { 0x00140350,   1},
+        { 0x00140480,   1},
+        { 0x001404a0,   1},
+        { 0x00140550,   1},
+        { 0x00140680,   1},
+        { 0x001406a0,   1},
+        { 0x00140750,   1},
+        { 0x00142028,   1},
+        { 0x00142280,   1},
+        { 0x001422a0,   1},
+        { 0x00142350,   1},
+        { 0x00142480,   1},
+        { 0x001424a0,   1},
+        { 0x00142550,   1},
+        { 0x00142680,   1},
+        { 0x001426a0,   1},
+        { 0x00142750,   1},
+        { 0x00144028,   1},
+        { 0x00144280,   1},
+        { 0x00144350,   1},
+        { 0x00144480,   1},
+        { 0x00144550,   1},
+        { 0x00144680,   1},
+        { 0x00144750,   1},
+        { 0x00146028,   1},
+        { 0x00146280,   1},
+        { 0x00146350,   1},
+        { 0x00146480,   1},
+        { 0x00146550,   1},
+        { 0x00146680,   1},
+        { 0x00146750,   1},
+        { 0x00148028,   1},
+        { 0x00148280,   1},
+        { 0x00148350,   1},
+        { 0x00148480,   1},
+        { 0x00148550,   1},
+        { 0x00148680,   1},
+        { 0x00148750,   1},
+        { 0x0014a028,   1},
+        { 0x0014a280,   1},
+        { 0x0014a350,   1},
+        { 0x0014a480,   1},
+        { 0x0014a550,   1},
+        { 0x0014a680,   1},
+        { 0x0014a750,   1},
+        { 0x0014c028,   1},
+        { 0x0014c280,   1},
+        { 0x0014c350,   1},
+        { 0x0014c480,   1},
+        { 0x0014c550,   1},
+        { 0x0014c680,   1},
+        { 0x0014c750,   1},
+        { 0x0014e028,   1},
+        { 0x0014e280,   1},
+        { 0x0014e350,   1},
+        { 0x0014e480,   1},
+        { 0x0014e550,   1},
+        { 0x0014e680,   1},
+        { 0x0014e750,   1},
+        { 0x00150028,   1},
+        { 0x00150280,   1},
+        { 0x00150350,   1},
+        { 0x00150480,   1},
+        { 0x00150550,   1},
+        { 0x00150680,   1},
+        { 0x00150750,   1},
+        { 0x00152028,   1},
+        { 0x00152280,   1},
+        { 0x00152350,   1},
+        { 0x00152480,   1},
+        { 0x00152550,   1},
+        { 0x00152680,   1},
+        { 0x00152750,   1},
+        { 0x00154028,   1},
+        { 0x00154280,   1},
+        { 0x00154350,   1},
+        { 0x00154480,   1},
+        { 0x00154550,   1},
+        { 0x00154680,   1},
+        { 0x00154750,   1},
+        { 0x00156028,   1},
+        { 0x00156280,   1},
+        { 0x00156350,   1},
+        { 0x00156480,   1},
+        { 0x00156550,   1},
+        { 0x00156680,   1},
+        { 0x00156750,   1},
+        { 0x0017e028,   1},
+        { 0x0017e280,   1},
+        { 0x0017e294,   1},
+        { 0x0017e29c,   2},
+        { 0x0017e2ac,   1},
+        { 0x0017e350,   1},
+        { 0x0017e39c,   1},
+        { 0x0017e480,   1},
+        { 0x0017e4a0,   1},
+        { 0x0017e550,   1},
+        { 0x0017e680,   1},
+        { 0x0017e6a0,   1},
+        { 0x0017e750,   1},
+        { 0x00180040,  41},
+        { 0x001800ec,   1},
+        { 0x001800f8,   7},
+        { 0x00180240,  41},
+        { 0x001802ec,   1},
+        { 0x001802f8,   7},
+        { 0x00180440,  41},
+        { 0x001804ec,   1},
+        { 0x001804f8,   7},
+        { 0x00180640,  41},
+        { 0x001806ec,   1},
+        { 0x001806f8,   7},
+        { 0x00180840,  41},
+        { 0x001808ec,   1},
+        { 0x001808f8,   7},
+        { 0x00180a40,  41},
+        { 0x00180aec,   1},
+        { 0x00180af8,   7},
+        { 0x00180c40,  41},
+        { 0x00180cec,   1},
+        { 0x00180cf8,   7},
+        { 0x00180e40,  41},
+        { 0x00180eec,   1},
+        { 0x00180ef8,   7},
+        { 0x00181040,  41},
+        { 0x001810ec,   1},
+        { 0x001810f8,   7},
+        { 0x00181240,  41},
+        { 0x001812ec,   1},
+        { 0x001812f8,   7},
+        { 0x00181440,  41},
+        { 0x001814ec,   1},
+        { 0x001814f8,   7},
+        { 0x00181640,  41},
+        { 0x001816ec,   1},
+        { 0x001816f8,   7},
+        { 0x00181840,  41},
+        { 0x001818ec,   1},
+        { 0x001818f8,   7},
+        { 0x00181a40,  41},
+        { 0x00181aec,   1},
+        { 0x00181af8,   7},
+        { 0x00181c40,  41},
+        { 0x00181cec,   1},
+        { 0x00181cf8,   7},
+        { 0x00181e40,  41},
+        { 0x00181eec,   1},
+        { 0x00181ef8,   7},
+        { 0x00182040,  41},
+        { 0x001820ec,   1},
+        { 0x001820f8,   7},
+        { 0x00182240,  41},
+        { 0x001822ec,   1},
+        { 0x001822f8,   7},
+        { 0x00182440,  41},
+        { 0x001824ec,   1},
+        { 0x001824f8,   7},
+        { 0x00182640,  41},
+        { 0x001826ec,   1},
+        { 0x001826f8,   7},
+        { 0x00182840,  41},
+        { 0x001828ec,   1},
+        { 0x001828f8,   7},
+        { 0x00182a40,  41},
+        { 0x00182aec,   1},
+        { 0x00182af8,   7},
+        { 0x00182c40,  41},
+        { 0x00182cec,   1},
+        { 0x00182cf8,   7},
+        { 0x00182e40,  41},
+        { 0x00182eec,   1},
+        { 0x00182ef8,   7},
+        { 0x00183040,  41},
+        { 0x001830ec,   1},
+        { 0x001830f8,   7},
+        { 0x00183240,  41},
+        { 0x001832ec,   1},
+        { 0x001832f8,   7},
+        { 0x00183440,  41},
+        { 0x001834ec,   1},
+        { 0x001834f8,   7},
+        { 0x00183640,  41},
+        { 0x001836ec,   1},
+        { 0x001836f8,   7},
+        { 0x00183840,  41},
+        { 0x001838ec,   1},
+        { 0x001838f8,   7},
+        { 0x00183a40,  41},
+        { 0x00183aec,   1},
+        { 0x00183af8,   7},
+        { 0x00183c40,  41},
+        { 0x00183cec,   1},
+        { 0x00183cf8,   7},
+        { 0x00183e40,  41},
+        { 0x00183eec,   1},
+        { 0x00183ef8,   7},
+        { 0x00184040,  41},
+        { 0x001840ec,   1},
+        { 0x001840f8,   7},
+        { 0x00184240,  41},
+        { 0x001842ec,   1},
+        { 0x001842f8,   7},
+        { 0x00184440,  41},
+        { 0x001844ec,   1},
+        { 0x001844f8,   7},
+        { 0x00184640,  41},
+        { 0x001846ec,   1},
+        { 0x001846f8,   7},
+        { 0x00184840,  41},
+        { 0x001848ec,   1},
+        { 0x001848f8,   7},
+        { 0x00184a40,  41},
+        { 0x00184aec,   1},
+        { 0x00184af8,   7},
+        { 0x00184c40,  41},
+        { 0x00184cec,   1},
+        { 0x00184cf8,   7},
+        { 0x00184e40,  41},
+        { 0x00184eec,   1},
+        { 0x00184ef8,   7},
+        { 0x00185040,  41},
+        { 0x001850ec,   1},
+        { 0x001850f8,   7},
+        { 0x00185240,  41},
+        { 0x001852ec,   1},
+        { 0x001852f8,   7},
+        { 0x00185440,  41},
+        { 0x001854ec,   1},
+        { 0x001854f8,   7},
+        { 0x00185640,  41},
+        { 0x001856ec,   1},
+        { 0x001856f8,   7},
+        { 0x00185840,  41},
+        { 0x001858ec,   1},
+        { 0x001858f8,   7},
+        { 0x00185a40,  41},
+        { 0x00185aec,   1},
+        { 0x00185af8,   7},
+        { 0x00185c40,  41},
+        { 0x00185cec,   1},
+        { 0x00185cf8,   7},
+        { 0x00185e40,  41},
+        { 0x00185eec,   1},
+        { 0x00185ef8,   7},
+        { 0x001a0040,  41},
+        { 0x001a00ec,   1},
+        { 0x001a00f8,   7},
+        { 0x001a0240,  41},
+        { 0x001a02ec,   1},
+        { 0x001a02f8,   7},
+        { 0x001a0440,  41},
+        { 0x001a04ec,   1},
+        { 0x001a04f8,   7},
+        { 0x001a0640,  41},
+        { 0x001a06ec,   1},
+        { 0x001a06f8,   7},
+        { 0x001a0840,  41},
+        { 0x001a08ec,   1},
+        { 0x001a08f8,   7},
+        { 0x001a0a40,  41},
+        { 0x001a0aec,   1},
+        { 0x001a0af8,   7},
+        { 0x001a0c40,  41},
+        { 0x001a0cec,   1},
+        { 0x001a0cf8,   7},
+        { 0x001a0e40,  41},
+        { 0x001a0eec,   1},
+        { 0x001a0ef8,   7},
+        { 0x001a1040,  41},
+        { 0x001a10ec,   1},
+        { 0x001a10f8,   7},
+        { 0x001a1240,  41},
+        { 0x001a12ec,   1},
+        { 0x001a12f8,   7},
+        { 0x001a1440,  41},
+        { 0x001a14ec,   1},
+        { 0x001a14f8,   7},
+        { 0x001a1640,  41},
+        { 0x001a16ec,   1},
+        { 0x001a16f8,   7},
+        { 0x001a1840,  41},
+        { 0x001a18ec,   1},
+        { 0x001a18f8,   7},
+        { 0x001a1a40,  41},
+        { 0x001a1aec,   1},
+        { 0x001a1af8,   7},
+        { 0x001a1c40,  41},
+        { 0x001a1cec,   1},
+        { 0x001a1cf8,   7},
+        { 0x001a1e40,  41},
+        { 0x001a1eec,   1},
+        { 0x001a1ef8,   7},
+        { 0x001a2040,  41},
+        { 0x001a20ec,   1},
+        { 0x001a20f8,   7},
+        { 0x001a2240,  41},
+        { 0x001a22ec,   1},
+        { 0x001a22f8,   7},
+        { 0x001a2440,  41},
+        { 0x001a24ec,   1},
+        { 0x001a24f8,   7},
+        { 0x001a2640,  41},
+        { 0x001a26ec,   1},
+        { 0x001a26f8,   7},
+        { 0x001a2840,  41},
+        { 0x001a28ec,   1},
+        { 0x001a28f8,   7},
+        { 0x001a2a40,  41},
+        { 0x001a2aec,   1},
+        { 0x001a2af8,   7},
+        { 0x001a2c40,  41},
+        { 0x001a2cec,   1},
+        { 0x001a2cf8,   7},
+        { 0x001a2e40,  41},
+        { 0x001a2eec,   1},
+        { 0x001a2ef8,   7},
+        { 0x001a3040,  41},
+        { 0x001a30ec,   1},
+        { 0x001a30f8,   7},
+        { 0x001a3240,  41},
+        { 0x001a32ec,   1},
+        { 0x001a32f8,   7},
+        { 0x001a3440,  41},
+        { 0x001a34ec,   1},
+        { 0x001a34f8,   7},
+        { 0x001a3640,  41},
+        { 0x001a36ec,   1},
+        { 0x001a36f8,   7},
+        { 0x001a3840,  41},
+        { 0x001a38ec,   1},
+        { 0x001a38f8,   7},
+        { 0x001a3a40,  41},
+        { 0x001a3aec,   1},
+        { 0x001a3af8,   7},
+        { 0x001a3c40,  41},
+        { 0x001a3cec,   1},
+        { 0x001a3cf8,   7},
+        { 0x001a3e40,  41},
+        { 0x001a3eec,   1},
+        { 0x001a3ef8,   7},
+        { 0x001a4040,  41},
+        { 0x001a40ec,   1},
+        { 0x001a40f8,   7},
+        { 0x001a4240,  41},
+        { 0x001a42ec,   1},
+        { 0x001a42f8,   7},
+        { 0x001a4440,  41},
+        { 0x001a44ec,   1},
+        { 0x001a44f8,   7},
+        { 0x001a4640,  41},
+        { 0x001a46ec,   1},
+        { 0x001a46f8,   7},
+        { 0x001a4840,  41},
+        { 0x001a48ec,   1},
+        { 0x001a48f8,   7},
+        { 0x001a4a40,  41},
+        { 0x001a4aec,   1},
+        { 0x001a4af8,   7},
+        { 0x001a4c40,  41},
+        { 0x001a4cec,   1},
+        { 0x001a4cf8,   7},
+        { 0x001a4e40,  41},
+        { 0x001a4eec,   1},
+        { 0x001a4ef8,   7},
+        { 0x001a5040,  41},
+        { 0x001a50ec,   1},
+        { 0x001a50f8,   7},
+        { 0x001a5240,  41},
+        { 0x001a52ec,   1},
+        { 0x001a52f8,   7},
+        { 0x001a5440,  41},
+        { 0x001a54ec,   1},
+        { 0x001a54f8,   7},
+        { 0x001a5640,  41},
+        { 0x001a56ec,   1},
+        { 0x001a56f8,   7},
+        { 0x001a5840,  41},
+        { 0x001a58ec,   1},
+        { 0x001a58f8,   7},
+        { 0x001a5a40,  41},
+        { 0x001a5aec,   1},
+        { 0x001a5af8,   7},
+        { 0x001a5c40,  41},
+        { 0x001a5cec,   1},
+        { 0x001a5cf8,   7},
+        { 0x001a5e40,  41},
+        { 0x001a5eec,   1},
+        { 0x001a5ef8,   7},
+        { 0x001b0040,  41},
+        { 0x001b00ec,   1},
+        { 0x001b00f8,   7},
+        { 0x001b0240,  41},
+        { 0x001b02ec,   1},
+        { 0x001b02f8,   7},
+        { 0x001b0440,  41},
+        { 0x001b04ec,   1},
+        { 0x001b04f8,   7},
+        { 0x001b0640,  41},
+        { 0x001b06ec,   1},
+        { 0x001b06f8,   7},
+        { 0x001b0840,  41},
+        { 0x001b08ec,   1},
+        { 0x001b08f8,   7},
+        { 0x001b0a40,  41},
+        { 0x001b0aec,   1},
+        { 0x001b0af8,   7},
+        { 0x001b0c40,  41},
+        { 0x001b0cec,   1},
+        { 0x001b0cf8,   7},
+        { 0x001b0e40,  41},
+        { 0x001b0eec,   1},
+        { 0x001b0ef8,   7},
+        { 0x001b4000,   1},
+        { 0x001b4008,   1},
+        { 0x001b4010,   3},
+        { 0x001b4020,   3},
+        { 0x001b4030,   3},
+        { 0x001b4040,   3},
+        { 0x001b4050,   3},
+        { 0x001b4060,   4},
+        { 0x001b4074,   7},
+        { 0x001b4094,   3},
+        { 0x001b40a4,   1},
+        { 0x001b4100,   6},
+        { 0x001b4124,   2},
+        { 0x001b8000,   1},
+        { 0x001b8008,   1},
+        { 0x001b8010,   3},
+        { 0x001b8200,   1},
+        { 0x001b8208,   1},
+        { 0x001b8210,   3},
+        { 0x001b8400,   1},
+        { 0x001b8408,   1},
+        { 0x001b8410,   3},
+        { 0x001b8600,   1},
+        { 0x001b8608,   1},
+        { 0x001b8610,   3},
+        { 0x001b8800,   1},
+        { 0x001b8808,   1},
+        { 0x001b8810,   3},
+        { 0x001b8a00,   1},
+        { 0x001b8a08,   1},
+        { 0x001b8a10,   3},
+        { 0x001bc000,   1},
+        { 0x001bc008,   1},
+        { 0x001bc010,   3},
+        { 0x001bc200,   1},
+        { 0x001bc208,   1},
+        { 0x001bc210,   3},
+        { 0x001bc400,   1},
+        { 0x001bc408,   1},
+        { 0x001bc410,   3},
+        { 0x001bc600,   1},
+        { 0x001bc608,   1},
+        { 0x001bc610,   3},
+        { 0x001bc800,   1},
+        { 0x001bc808,   1},
+        { 0x001bc810,   3},
+        { 0x001bca00,   1},
+        { 0x001bca08,   1},
+        { 0x001bca10,   3},
+        { 0x001bd218,   1},
+        { 0x001be000,   1},
+        { 0x001be008,   1},
+        { 0x001be010,   3},
+        { 0x001be218,   1},
+        { 0x001bf218,   1},
+        { 0x001c0218,   1},
+        { 0x001c1218,   1},
+        { 0x001c80a8,   1},
+        { 0x001c9100,   1},
+        { 0x001cc0a8,   1},
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+        { 0x0052d6e8,   1},
+        { 0x0052d6f0,  28},
+        { 0x0052d770,   1},
+        { 0x0052d778,   2},
+        { 0x0052d798,   2},
+        { 0x0052d7dc,   1},
+        { 0x0052d854,   1},
+        { 0x0052dab0,   1},
+        { 0x0052dab8,   3},
+        { 0x0052dc0c,   1},
+        { 0x0052dc8c,   2},
+        { 0x0052dd00,   1},
+        { 0x0052dd08,   2},
+        { 0x0052de00,  11},
+        { 0x0052de34,   2},
+        { 0x0052de44,  11},
+        { 0x0052de74,  10},
+        { 0x0052dea4,   1},
+        { 0x0052deac,   2},
+        { 0x0052dee8,   1},
+        { 0x0052def0,  28},
+        { 0x0052df70,   1},
+        { 0x0052df78,   2},
+        { 0x0052df98,   2},
+        { 0x0052dfdc,   1},
+        { 0x0052e054,   1},
+        { 0x0052e2b0,   1},
+        { 0x0052e2b8,   3},
+        { 0x0052e40c,   1},
+        { 0x0052e48c,   2},
+        { 0x0052e500,   1},
+        { 0x0052e508,   2},
+        { 0x0052e600,  11},
+        { 0x0052e634,   2},
+        { 0x0052e644,  11},
+        { 0x0052e674,  10},
+        { 0x0052e6a4,   1},
+        { 0x0052e6ac,   2},
+        { 0x0052e6e8,   1},
+        { 0x0052e6f0,  28},
+        { 0x0052e770,   1},
+        { 0x0052e778,   2},
+        { 0x0052e798,   2},
+        { 0x0052e7dc,   1},
+        { 0x00900100,   1},
+        { 0x00904100,   1},
+        { 0x00908100,   1},
+        { 0x0090c100,   1},
+        { 0x00910100,   1},
+        { 0x00914100,   1},
+        { 0x009a0100,   1},
+};
+
+
+static const u32 gp106_global_whitelist_ranges_count =
+        ARRAY_SIZE(gp106_global_whitelist_ranges);
+
+/* context */
+
+/* runcontrol */
+static const u32 gp106_runcontrol_whitelist[] = {
+};
+static const u32 gp106_runcontrol_whitelist_count =
+        ARRAY_SIZE(gp106_runcontrol_whitelist);
+
+static const struct regop_offset_range gp106_runcontrol_whitelist_ranges[] = {
+};
+static const u32 gp106_runcontrol_whitelist_ranges_count =
+        ARRAY_SIZE(gp106_runcontrol_whitelist_ranges);
+
+
+/* quad ctl */
+static const u32 gp106_qctl_whitelist[] = {
+};
+static const u32 gp106_qctl_whitelist_count =
+        ARRAY_SIZE(gp106_qctl_whitelist);
+
+static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = {
+};
+static const u32 gp106_qctl_whitelist_ranges_count =
+        ARRAY_SIZE(gp106_qctl_whitelist_ranges);
+
+static const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
+{
+        return gp106_global_whitelist_ranges;
+}
+
+static int gp106_get_global_whitelist_ranges_count(void)
+{
+        return gp106_global_whitelist_ranges_count;
+}
+
+static const struct regop_offset_range *gp106_get_context_whitelist_ranges(void)
+{
+        return gp106_global_whitelist_ranges;
+}
+
+static int gp106_get_context_whitelist_ranges_count(void)
+{
+        return gp106_global_whitelist_ranges_count;
+}
+
+static const u32 *gp106_get_runcontrol_whitelist(void)
+{
+        return gp106_runcontrol_whitelist;
+}
+
+static int gp106_get_runcontrol_whitelist_count(void)
+{
+        return gp106_runcontrol_whitelist_count;
+}
+
+static const
+struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void)
+{
+        return gp106_runcontrol_whitelist_ranges;
+}
+
+static int gp106_get_runcontrol_whitelist_ranges_count(void)
+{
+        return gp106_runcontrol_whitelist_ranges_count;
+}
+
+static const u32 *gp106_get_qctl_whitelist(void)
+{
+        return gp106_qctl_whitelist;
+}
+
+static int gp106_get_qctl_whitelist_count(void)
+{
+        return gp106_qctl_whitelist_count;
+}
+
+static const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void)
+{
+        return gp106_qctl_whitelist_ranges;
+}
+
+static int gp106_get_qctl_whitelist_ranges_count(void)
+{
+        return gp106_qctl_whitelist_ranges_count;
+}
+
+static int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
+{
+        /* Not needed on gp106 */
+        return 0;
+}
+
+void gp106_init_regops(struct gpu_ops *gops)
+{
+        gops->regops.get_global_whitelist_ranges =
+                gp106_get_global_whitelist_ranges;
+        gops->regops.get_global_whitelist_ranges_count =
+                gp106_get_global_whitelist_ranges_count;
+
+        gops->regops.get_context_whitelist_ranges =
+                gp106_get_context_whitelist_ranges;
+        gops->regops.get_context_whitelist_ranges_count =
+                gp106_get_context_whitelist_ranges_count;
+
+        gops->regops.get_runcontrol_whitelist =
+                gp106_get_runcontrol_whitelist;
+        gops->regops.get_runcontrol_whitelist_count =
+                gp106_get_runcontrol_whitelist_count;
+
+        gops->regops.get_runcontrol_whitelist_ranges =
+                gp106_get_runcontrol_whitelist_ranges;
+        gops->regops.get_runcontrol_whitelist_ranges_count =
+                gp106_get_runcontrol_whitelist_ranges_count;
+
+        gops->regops.get_qctl_whitelist =
+                gp106_get_qctl_whitelist;
+        gops->regops.get_qctl_whitelist_count =
+                gp106_get_qctl_whitelist_count;
+
+        gops->regops.get_qctl_whitelist_ranges =
+                gp106_get_qctl_whitelist_ranges;
+        gops->regops.get_qctl_whitelist_ranges_count =
+                gp106_get_qctl_whitelist_ranges_count;
+
+        gops->regops.apply_smpc_war =
+                gp106_apply_smpc_war;
+}
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.h b/drivers/gpu/nvgpu/gp106/regops_gp106.h
new file mode 100644
index 00000000..7f6b6861
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.h
@@ -0,0 +1,24 @@
+/*
+ *
+ * Tegra GP106 GPU Debugger Driver Register Ops
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __REGOPS_GP106_H_
+#define __REGOPS_GP106_H_
+
+void gp106_init_regops(struct gpu_ops *gops);
+
+#endif /* __REGOPS_GP106_H_ */
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
new file mode 100644
index 00000000..8f34edd1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>        /* for udelay */
+#include <linux/clk.h>
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+
+#include "gm206/pmu_gm206.h"
+#include "gm20b/pmu_gm20b.h"
+#include "gp10b/pmu_gp10b.h"
+#include "gp106/pmu_gp106.h"
+#include "gp106/acr_gp106.h"
+#include "gp106/hw_mc_gp106.h"
+#include "gp106/hw_pwr_gp106.h"
+#include "gp106/hw_psec_gp106.h"
+#include "sec2_gp106.h"
+#include "acr.h"
+
+/*Defines*/
+#define gm20b_dbg_pmu(fmt, arg...) \
+        gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
+
+int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout)
+{
+        u32 data = 0;
+        unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+
+        while (time_before(jiffies, end_jiffies) ||
+                        !tegra_platform_is_silicon()) {
+                gk20a_writel(g, psec_falcon_irqsclr_r(),
+                             gk20a_readl(g, psec_falcon_irqsclr_r()) | (0x10));
+                data = gk20a_readl(g, psec_falcon_irqstat_r());
+                if ((data & psec_falcon_irqstat_halt_true_f()) !=
+                        psec_falcon_irqstat_halt_true_f())
+                        /*halt irq is clear*/
+                        break;
+                timeout--;
+                udelay(1);
+        }
+        if (timeout == 0)
+                return -EBUSY;
+        return 0;
+}
+
+int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
+{
+        u32 data = 0;
+        int completion = -EBUSY;
+        unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+
+        while (time_before(jiffies, end_jiffies) ||
+                        !tegra_platform_is_silicon()) {
+                data = gk20a_readl(g, psec_falcon_cpuctl_r());
+                if (data & psec_falcon_cpuctl_halt_intr_m()) {
+                        /*CPU is halted break*/
+                        completion = 0;
+                        break;
+                }
+                udelay(1);
+        }
+        if (completion){
+                gk20a_err(dev_from_gk20a(g), "ACR boot timed out");
+        }
+        else {
+
+                g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r());
+                gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities);
+                data = gk20a_readl(g, psec_falcon_mailbox0_r());
+                if (data) {
+
+                        gk20a_err(dev_from_gk20a(g),
+                                "ACR boot failed, err %x", data);
+                        completion = -EAGAIN;
+                }
+        }
+
+        init_pmu_setup_hw1(g);
+
+        return completion;
+}
+
+void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
+                u32 dst, u8 *src, u32 size, u8 port)
+{
+        struct gk20a *g = gk20a_from_pmu(pmu);
+        u32 i, words, bytes;
+        u32 data, addr_mask;
+        u32 *src_u32 = (u32*)src;
+
+        if (size == 0) {
+                gk20a_err(dev_from_gk20a(g),
+                        "size is zero");
+                return;
+        }
+
+        if (dst & 0x3) {
+                gk20a_err(dev_from_gk20a(g),
+                        "dst (0x%08x) not 4-byte aligned", dst);
+                return;
+        }
+
+        mutex_lock(&pmu->pmu_copy_lock);
+
+        words = size >> 2;
+        bytes = size & 0x3;
+
+        addr_mask = psec_falcon_dmemc_offs_m() |
+                    psec_falcon_dmemc_blk_m();
+
+        dst &= addr_mask;
+
+        gk20a_writel(g, psec_falcon_dmemc_r(port),
+                dst | psec_falcon_dmemc_aincw_f(1));
+
+        for (i = 0; i < words; i++)
+                gk20a_writel(g, psec_falcon_dmemd_r(port), src_u32[i]);
+
+        if (bytes > 0) {
+                data = 0;
+                for (i = 0; i < bytes; i++)
+                        ((u8 *)&data)[i] = src[(words << 2) + i];
+                gk20a_writel(g, psec_falcon_dmemd_r(port), data);
+        }
+
+        data = gk20a_readl(g, psec_falcon_dmemc_r(port)) & addr_mask;
+        size = ALIGN(size, 4);
+        if (data != dst + size) {
+                gk20a_err(dev_from_gk20a(g),
+                        "copy failed. bytes written %d, expected %d",
+                        data - dst, size);
+        }
+        mutex_unlock(&pmu->pmu_copy_lock);
+        return;
+}
+
+int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
+        void *desc, u32 bl_sz)
+{
+        struct gk20a *g = gk20a_from_pmu(pmu);
+        struct acr_desc *acr = &g->acr;
+        struct mm_gk20a *mm = &g->mm;
+        u32 imem_dst_blk = 0;
+        u32 virt_addr = 0;
+        u32 tag = 0;
+        u32 index = 0;
+        struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc;
+        u32 *bl_ucode;
+        u32 data = 0;
+
+        gk20a_dbg_fn("");
+
+        /* SEC2 Config */
+        gk20a_writel(g, psec_falcon_itfen_r(),
+                        gk20a_readl(g, psec_falcon_itfen_r()) |
+                        psec_falcon_itfen_ctxen_enable_f());
+
+        gk20a_writel(g, psec_falcon_nxtctx_r(),
+                        pwr_pmu_new_instblk_ptr_f(
+                        gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+                        pwr_pmu_new_instblk_valid_f(1) |
+                        gk20a_aperture_mask(g, &mm->pmu.inst_block,
+                                pwr_pmu_new_instblk_target_sys_coh_f(),
+                                pwr_pmu_new_instblk_target_fb_f()));
+
+        data = gk20a_readl(g, psec_falcon_debug1_r());
+        data |= psec_falcon_debug1_ctxsw_mode_m();
+        gk20a_writel(g, psec_falcon_debug1_r(), data);
+
+        data = gk20a_readl(g, psec_falcon_engctl_r());
+        data |= (1 << 3);
+        gk20a_writel(g, psec_falcon_engctl_r(), data);
+
+        /* TBD: load all other surfaces */
+        /*copy bootloader interface structure to dmem*/
+        gk20a_writel(g, psec_falcon_dmemc_r(0),
+                        psec_falcon_dmemc_offs_f(0) |
+                        psec_falcon_dmemc_blk_f(0)  |
+                        psec_falcon_dmemc_aincw_f(1));
+        sec2_copy_to_dmem(pmu, 0, (u8 *)desc,
+                sizeof(struct flcn_bl_dmem_desc), 0);
+        /*TODO This had to be copied to bl_desc_dmem_load_off, but since
+         * this is 0, so ok for now*/
+
+        /* Now copy bootloader to TOP of IMEM */
+        imem_dst_blk = (psec_falcon_hwcfg_imem_size_v(
+                        gk20a_readl(g, psec_falcon_hwcfg_r()))) - bl_sz/256;
+
+        /* Set Auto-Increment on write */
+        gk20a_writel(g, psec_falcon_imemc_r(0),
+                        psec_falcon_imemc_offs_f(0) |
+                        psec_falcon_imemc_blk_f(imem_dst_blk)  |
+                        psec_falcon_imemc_aincw_f(1));
+        virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
+        tag = virt_addr >> 8; /* tag is always 256B aligned */
+        bl_ucode = (u32 *)(acr->hsbl_ucode.cpu_va);
+        for (index = 0; index < bl_sz/4; index++) {
+                if ((index % 64) == 0) {
+                        gk20a_writel(g, psec_falcon_imemt_r(0),
+                                (tag & 0xffff) << 0);
+                        tag++;
+                }
+                gk20a_writel(g, psec_falcon_imemd_r(0),
+                                bl_ucode[index] & 0xffffffff);
+        }
+        gk20a_writel(g, psec_falcon_imemt_r(0), (0 & 0xffff) << 0);
+
+        gm20b_dbg_pmu("Before starting falcon with BL\n");
+
+        gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5);
+
+        gk20a_writel(g, psec_falcon_bootvec_r(),
+                        psec_falcon_bootvec_vec_f(virt_addr));
+
+        gk20a_writel(g, psec_falcon_cpuctl_r(),
+                        psec_falcon_cpuctl_startcpu_f(1));
+
+        return 0;
+}
+
+void sec_enable_irq(struct pmu_gk20a *pmu, bool enable)
+{
+        struct gk20a *g = gk20a_from_pmu(pmu);
+
+        gk20a_dbg_fn("");
+
+        gk20a_writel(g, psec_falcon_irqmclr_r(),
+                psec_falcon_irqmclr_gptmr_f(1)  |
+                psec_falcon_irqmclr_wdtmr_f(1)  |
+                psec_falcon_irqmclr_mthd_f(1)   |
+                psec_falcon_irqmclr_ctxsw_f(1)  |
+                psec_falcon_irqmclr_halt_f(1)   |
+                psec_falcon_irqmclr_exterr_f(1) |
+                psec_falcon_irqmclr_swgen0_f(1) |
+                psec_falcon_irqmclr_swgen1_f(1) |
+                psec_falcon_irqmclr_ext_f(0xff));
+
+        if (enable) {
+                /* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */
+                gk20a_writel(g, psec_falcon_irqdest_r(),
+                        psec_falcon_irqdest_host_gptmr_f(0)    |
+                        psec_falcon_irqdest_host_wdtmr_f(1)    |
+                        psec_falcon_irqdest_host_mthd_f(0)     |
+                        psec_falcon_irqdest_host_ctxsw_f(0)    |
+                        psec_falcon_irqdest_host_halt_f(1)     |
+                        psec_falcon_irqdest_host_exterr_f(0)   |
+                        psec_falcon_irqdest_host_swgen0_f(1)   |
+                        psec_falcon_irqdest_host_swgen1_f(0)   |
+                        psec_falcon_irqdest_host_ext_f(0xff)   |
+                        psec_falcon_irqdest_target_gptmr_f(1)  |
+                        psec_falcon_irqdest_target_wdtmr_f(0)  |
+                        psec_falcon_irqdest_target_mthd_f(0)   |
+                        psec_falcon_irqdest_target_ctxsw_f(0)  |
+                        psec_falcon_irqdest_target_halt_f(0)   |
+                        psec_falcon_irqdest_target_exterr_f(0) |
+                        psec_falcon_irqdest_target_swgen0_f(0) |
+                        psec_falcon_irqdest_target_swgen1_f(1) |
+                        psec_falcon_irqdest_target_ext_f(0xff));
+
+                /* 0=disable, 1=enable */
+                gk20a_writel(g, psec_falcon_irqmset_r(),
+                        psec_falcon_irqmset_gptmr_f(1)  |
+                        psec_falcon_irqmset_wdtmr_f(1)  |
+                        psec_falcon_irqmset_mthd_f(0)   |
+                        psec_falcon_irqmset_ctxsw_f(0)  |
+                        psec_falcon_irqmset_halt_f(1)   |
+                        psec_falcon_irqmset_exterr_f(1) |
+                        psec_falcon_irqmset_swgen0_f(1) |
+                        psec_falcon_irqmset_swgen1_f(1));
+
+        }
+
+        gk20a_dbg_fn("done");
+}
+
+void init_pmu_setup_hw1(struct gk20a *g)
+{
+        struct mm_gk20a *mm = &g->mm;
+        struct pmu_gk20a *pmu = &g->pmu;
+        struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+
+        /* PMU TRANSCFG */
+        /* setup apertures - virtual */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+                        pwr_fbif_transcfg_mem_type_virtual_f());
+        /* setup apertures - physical */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_coherent_sysmem_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+
+        /* PMU Config */
+        gk20a_writel(g, pwr_falcon_itfen_r(),
+                                gk20a_readl(g, pwr_falcon_itfen_r()) |
+                                pwr_falcon_itfen_ctxen_enable_f());
+        gk20a_writel(g, pwr_pmu_new_instblk_r(),
+                                pwr_pmu_new_instblk_ptr_f(
+                                        gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+                                pwr_pmu_new_instblk_valid_f(1) |
+                                gk20a_aperture_mask(g, &mm->pmu.inst_block,
+                                        pwr_pmu_new_instblk_target_sys_coh_f(),
+                                        pwr_pmu_new_instblk_target_fb_f()));
+
+        /*Copying pmu cmdline args*/
+        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
+                                clk_get_rate(platform->clk[1]));
+        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
+                pmu, GK20A_PMU_TRACE_BUFSIZE);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
+                pmu, GK20A_PMU_DMAIDX_VIRT);
+
+        pmu_copy_to_dmem(pmu, g->acr.pmu_args,
+                        (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
+                        g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
+
+}
+
+int init_sec2_setup_hw1(struct gk20a *g,
+                void *desc, u32 bl_sz)
+{
+        struct pmu_gk20a *pmu = &g->pmu;
+        int err;
+        u32 data = 0;
+
+        gk20a_dbg_fn("");
+
+        mutex_lock(&pmu->isr_mutex);
+        g->ops.pmu.reset(g);
+        pmu->isr_enabled = true;
+        mutex_unlock(&pmu->isr_mutex);
+
+        data = gk20a_readl(g, psec_fbif_ctl_r());
+        data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f();
+        gk20a_writel(g, psec_fbif_ctl_r(), data);
+
+        data = gk20a_readl(g, psec_falcon_dmactl_r());
+        data &= ~(psec_falcon_dmactl_require_ctx_f(1));
+        gk20a_writel(g, psec_falcon_dmactl_r(), data);
+
+        /* setup apertures - virtual */
+        gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+                        psec_fbif_transcfg_mem_type_physical_f() |
+                        psec_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+                        psec_fbif_transcfg_mem_type_virtual_f());
+        /* setup apertures - physical */
+        gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+                        psec_fbif_transcfg_mem_type_physical_f() |
+                        psec_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+                        psec_fbif_transcfg_mem_type_physical_f() |
+                        psec_fbif_transcfg_target_coherent_sysmem_f());
+        gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+                        psec_fbif_transcfg_mem_type_physical_f() |
+                        psec_fbif_transcfg_target_noncoherent_sysmem_f());
+
+        /*disable irqs for hs falcon booting as we will poll for halt*/
+        mutex_lock(&pmu->isr_mutex);
+        pmu_enable_irq(pmu, false);
+        sec_enable_irq(pmu, false);
+        pmu->isr_enabled = false;
+        mutex_unlock(&pmu->isr_mutex);
+        err = bl_bootstrap_sec2(pmu, desc, bl_sz);
+        if (err)
+                return err;
+
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
new file mode 100644
index 00000000..336bb0f0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __SEC2_H_
+#define __SEC2_H_
+
+int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
+int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
+void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
+                u32 dst, u8 *src, u32 size, u8 port);
+void sec2_dump_falcon_stats(struct pmu_gk20a *pmu);
+int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
+        void *desc, u32 bl_sz);
+void sec_enable_irq(struct pmu_gk20a *pmu, bool enable);
+void init_pmu_setup_hw1(struct gk20a *g);
+int init_sec2_setup_hw1(struct gk20a *g,
+                void *desc, u32 bl_sz);
+
+#endif /*__SEC2_H_*/
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.c b/drivers/gpu/nvgpu/gp106/therm_gp106.c
new file mode 100644
index 00000000..7bdf0b9e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/therm_gp106.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "therm_gp106.h"
+#include <linux/debugfs.h>
+#include "hw_therm_gp106.h"
+
+static void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8)
+{
+        *max_24_8 = (0x87 << 8);
+        *min_24_8 = ((-216) << 8);
+}
+
+static int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
+{
+        int err = 0;
+        u32 readval;
+
+        readval = gk20a_readl(g, therm_temp_sensor_tsense_r());
+
+        if (!(therm_temp_sensor_tsense_state_v(readval) &
+                therm_temp_sensor_tsense_state_valid_v())) {
+                gk20a_err(dev_from_gk20a(g),
+                        "Attempt to read temperature while sensor is OFF!\n");
+                err = -EINVAL;
+        } else if (therm_temp_sensor_tsense_state_v(readval) &
+                therm_temp_sensor_tsense_state_shadow_v()) {
+                gk20a_err(dev_from_gk20a(g),
+                        "Reading temperature from SHADOWed sensor!\n");
+        }
+
+        // Convert from F9.5 -> F27.5 -> F24.8.
+        readval &= therm_temp_sensor_tsense_fixed_point_m();
+
+        *temp_f24_8 = readval;
+
+        return err;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int therm_get_internal_sensor_curr_temp(void *data, u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        u32 readval;
+        int err;
+
+        err = gp106_get_internal_sensor_curr_temp(g, &readval);
+        if (!err)
+                *val = readval;
+
+        return err;
+}
+DEFINE_SIMPLE_ATTRIBUTE(therm_ctrl_fops, therm_get_internal_sensor_curr_temp, NULL, "%llu\n");
+
+static void gp106_therm_debugfs_init(struct gk20a *g) {
+        struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+        struct dentry *dbgentry;
+
+        dbgentry = debugfs_create_file(
+                "temp", S_IRUGO, platform->debugfs, g, &therm_ctrl_fops);
+        if (!dbgentry)
+                gk20a_err(dev_from_gk20a(g), "debugfs entry create failed for therm_curr_temp");
+}
+#endif
+
+static int gp106_elcg_init_idle_filters(struct gk20a *g)
+{
+        u32 gate_ctrl, idle_filter;
+        u32 engine_id;
+        u32 active_engine_id = 0;
+        struct fifo_gk20a *f = &g->fifo;
+
+        gk20a_dbg_fn("");
+
+        for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
+                active_engine_id = f->active_engines_list[engine_id];
+                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
+
+                if (tegra_platform_is_linsim()) {
+                        gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_delay_after_m(),
+                                therm_gate_ctrl_eng_delay_after_f(4));
+                }
+
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_idle_filt_exp_m(),
+                        therm_gate_ctrl_eng_idle_filt_exp_f(2));
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_idle_filt_mant_m(),
+                        therm_gate_ctrl_eng_idle_filt_mant_f(1));
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_delay_before_m(),
+                        therm_gate_ctrl_eng_delay_before_f(0));
+                gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
+        }
+
+        /* default fecs_idle_filter to 0 */
+        idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
+        idle_filter &= ~therm_fecs_idle_filter_value_m();
+        gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
+        /* default hubmmu_idle_filter to 0 */
+        idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
+        idle_filter &= ~therm_hubmmu_idle_filter_value_m();
+        gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
+
+        gk20a_dbg_fn("done");
+        return 0;
+}
+
+void gp106_init_therm_ops(struct gpu_ops *gops) {
+#ifdef CONFIG_DEBUG_FS
+        gops->therm.therm_debugfs_init = gp106_therm_debugfs_init;
+#endif
+        gops->therm.elcg_init_idle_filters = gp106_elcg_init_idle_filters;
+        gops->therm.get_internal_sensor_curr_temp = gp106_get_internal_sensor_curr_temp;
+        gops->therm.get_internal_sensor_limits =
+                        gp106_get_internal_sensor_limits;
+}
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.h b/drivers/gpu/nvgpu/gp106/therm_gp106.h
new file mode 100644
index 00000000..6db17c47
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/therm_gp106.h
@@ -0,0 +1,22 @@
+/*
+ * general thermal control structures & definitions
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_THERM_GP106_H
+#define NVGPU_THERM_GP106_H
+
+#include "gk20a/gk20a.h"
+
+void gp106_init_therm_ops(struct gpu_ops *gops);
+#endif
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.c b/drivers/gpu/nvgpu/gp106/xve_gp106.c
new file mode 100644
index 00000000..23a02fbd
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/xve_gp106.c
@@ -0,0 +1,623 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/debugfs.h>
+
+#include "gk20a/gk20a.h"
+#include "gm206/bios_gm206.h"
+#include "gp106/xve_gp106.h"
+
+#include "gp106/hw_xp_gp106.h"
+#include "gp106/hw_xve_gp106.h"
+
+/**
+ * Init a timer and place the timeout data in @timeout.
+ */
+static void init_timeout(u32 timeout_ms, u32 *timeout)
+{
+        *timeout = jiffies + msecs_to_jiffies(timeout_ms);
+}
+
+/**
+ * Returns 1 if the current time is after @timeout i.e: the timer timed
+ * out. Returns 0 if the timer still has time left.
+ */
+static int check_timeout(u32 *timeout)
+{
+        unsigned long now = jiffies;
+        unsigned long timeout_l = (unsigned long)*timeout;
+
+        if (time_after(now, timeout_l))
+                return 1;
+
+        return 0;
+}
+
+static void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val)
+{
+        gk20a_writel(g, NV_PCFG + reg, val);
+}
+
+static u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg)
+{
+        return gk20a_readl(g, NV_PCFG + reg);
+}
+
+/**
+ * Places one of:
+ *
+ *   %GPU_XVE_SPEED_2P5
+ *   %GPU_XVE_SPEED_5P0
+ *   %GPU_XVE_SPEED_8P0
+ *
+ * in the u32 pointed to by @xve_link_speed. If for some reason an unknown PCIe
+ * bus speed is detected then *@xve_link_speed is not touched and -ENODEV is
+ * returned.
+ */
+static int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed)
+{
+        u32 status;
+        u32 link_speed, real_link_speed = 0;
+
+        status = g->ops.xve.xve_readl(g, xve_link_control_status_r());
+
+        link_speed = xve_link_control_status_link_speed_v(status);
+
+        /*
+         * Can't use a switch statement becuase switch statements dont work with
+         * function calls.
+         */
+        if (link_speed == xve_link_control_status_link_speed_link_speed_2p5_v())
+                real_link_speed = GPU_XVE_SPEED_2P5;
+        if (link_speed == xve_link_control_status_link_speed_link_speed_5p0_v())
+                real_link_speed = GPU_XVE_SPEED_5P0;
+        if (link_speed == xve_link_control_status_link_speed_link_speed_8p0_v())
+                real_link_speed = GPU_XVE_SPEED_8P0;
+
+        if (!real_link_speed) {
+                pr_warn("%s: Unknown PCIe bus speed!\n", __func__);
+                return -ENODEV;
+        }
+
+        *xve_link_speed = real_link_speed;
+        return 0;
+}
+
+/**
+ * Set the mask for L0s in the XVE.
+ *
+ * When @status is non-zero the mask for L0s is set which _disables_ L0s. When
+ * @status is zero L0s is no longer masked and may be enabled.
+ */
+static void set_xve_l0s_mask(struct gk20a *g, bool status)
+{
+        u32 xve_priv;
+        u32 status_bit = status ? 1 : 0;
+
+        xve_priv = g->ops.xve.xve_readl(g, xve_priv_xv_r());
+
+        xve_priv = set_field(xve_priv,
+                  xve_priv_xv_cya_l0s_enable_m(),
+                  xve_priv_xv_cya_l0s_enable_f(status_bit));
+
+        g->ops.xve.xve_writel(g, xve_priv_xv_r(), xve_priv);
+}
+
+/**
+ * Set the mask for L1 in the XVE.
+ *
+ * When @status is non-zero the mask for L1 is set which _disables_ L0s. When
+ * @status is zero L1 is no longer masked and may be enabled.
+ */
+static void set_xve_l1_mask(struct gk20a *g, int status)
+{
+        u32 xve_priv;
+        u32 status_bit = status ? 1 : 0;
+
+        xve_priv = g->ops.xve.xve_readl(g, xve_priv_xv_r());
+
+        xve_priv = set_field(xve_priv,
+                  xve_priv_xv_cya_l1_enable_m(),
+                  xve_priv_xv_cya_l1_enable_f(status_bit));
+
+        g->ops.xve.xve_writel(g, xve_priv_xv_r(), xve_priv);
+}
+
+/**
+ * When doing the speed change disable power saving features.
+ */
+static void disable_aspm_gp106(struct gk20a *g)
+{
+        u32 xve_priv;
+
+        xve_priv = g->ops.xve.xve_readl(g, xve_priv_xv_r());
+
+        /*
+         * Store prior ASPM state so we can restore it later on.
+         */
+        g->xve_l0s = xve_priv_xv_cya_l0s_enable_v(xve_priv);
+        g->xve_l1  = xve_priv_xv_cya_l1_enable_v(xve_priv);
+
+        set_xve_l0s_mask(g, true);
+        set_xve_l1_mask(g, true);
+}
+
+/**
+ * Restore the state saved by disable_aspm_gp106().
+ */
+static void enable_aspm_gp106(struct gk20a *g)
+{
+        set_xve_l0s_mask(g, g->xve_l0s);
+        set_xve_l1_mask(g, g->xve_l1);
+}
+
+/*
+ * Error checking is done in xve_set_speed_gp106.
+ */
+static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
+{
+        u32 current_link_speed, new_link_speed;
+        u32 dl_mgr, saved_dl_mgr;
+        u32 pl_link_config;
+        u32 link_control_status, link_speed_setting, link_width;
+        u32 timeout;
+        int attempts = 10, err_status = 0;
+
+        g->ops.xve.get_speed(g, &current_link_speed);
+        xv_sc_dbg(PRE_CHANGE, "Executing PCIe link change.");
+        xv_sc_dbg(PRE_CHANGE, "  Current speed:  %s",
+                  xve_speed_to_str(current_link_speed));
+        xv_sc_dbg(PRE_CHANGE, "  Next speed:     %s",
+                  xve_speed_to_str(next_link_speed));
+        xv_sc_dbg(PRE_CHANGE, "  PL_LINK_CONFIG: 0x%08x",
+                  gk20a_readl(g, xp_pl_link_config_r(0)));
+
+        xv_sc_dbg(DISABLE_ASPM, "Disabling ASPM...");
+        disable_aspm_gp106(g);
+        xv_sc_dbg(DISABLE_ASPM, "  Done!");
+
+        xv_sc_dbg(DL_SAFE_MODE, "Putting DL in safe mode...");
+        saved_dl_mgr = gk20a_readl(g, xp_dl_mgr_r(0));
+
+        /*
+         * Put the DL in safe mode.
+         */
+        dl_mgr = saved_dl_mgr;
+        dl_mgr |= xp_dl_mgr_safe_timing_f(1);
+        gk20a_writel(g, xp_dl_mgr_r(0), dl_mgr);
+        xv_sc_dbg(DL_SAFE_MODE, "  Done!");
+
+        init_timeout(GPU_XVE_TIMEOUT_MS, &timeout);
+
+        xv_sc_dbg(CHECK_LINK, "Checking for link idle...");
+        while (1) {
+                pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+                if ((xp_pl_link_config_ltssm_status_f(pl_link_config) ==
+                     xp_pl_link_config_ltssm_status_idle_v()) &&
+                    (xp_pl_link_config_ltssm_directive_f(pl_link_config) ==
+                     xp_pl_link_config_ltssm_directive_normal_operations_v()))
+                        break;
+
+                if (check_timeout(&timeout)) {
+                        err_status = -ETIMEDOUT;
+                        break;
+                }
+        }
+
+        if (err_status == -ETIMEDOUT)
+                /* TODO: debug message. */
+                goto done;
+
+        xv_sc_dbg(CHECK_LINK, "  Done");
+
+        xv_sc_dbg(LINK_SETTINGS, "Preparing next link settings");
+        pl_link_config &= ~xp_pl_link_config_max_link_rate_m();
+        switch (next_link_speed) {
+        case GPU_XVE_SPEED_2P5:
+                link_speed_setting =
+                        xve_link_control_status_link_speed_link_speed_2p5_v();
+                pl_link_config |= xp_pl_link_config_max_link_rate_f(
+                        xp_pl_link_config_max_link_rate_2500_mtps_v());
+                break;
+        case GPU_XVE_SPEED_5P0:
+                link_speed_setting =
+                        xve_link_control_status_link_speed_link_speed_5p0_v();
+                pl_link_config |= xp_pl_link_config_max_link_rate_f(
+                        xp_pl_link_config_max_link_rate_5000_mtps_v());
+                break;
+        case GPU_XVE_SPEED_8P0:
+                link_speed_setting =
+                        xve_link_control_status_link_speed_link_speed_8p0_v();
+                pl_link_config |= xp_pl_link_config_max_link_rate_f(
+                        xp_pl_link_config_max_link_rate_8000_mtps_v());
+                break;
+        default:
+                BUG(); /* Should never be hit. */
+        }
+
+        link_control_status =
+                g->ops.xve.xve_readl(g, xve_link_control_status_r());
+        link_width = xve_link_control_status_link_width_v(link_control_status);
+
+        pl_link_config &= ~xp_pl_link_config_target_tx_width_m();
+
+        /* Can't use a switch due to oddities in register definitions. */
+        if (link_width == xve_link_control_status_link_width_x1_v())
+                pl_link_config |= xp_pl_link_config_target_tx_width_f(
+                        xp_pl_link_config_target_tx_width_x1_v());
+        else if (link_width == xve_link_control_status_link_width_x2_v())
+                pl_link_config |= xp_pl_link_config_target_tx_width_f(
+                        xp_pl_link_config_target_tx_width_x2_v());
+        else if (link_width == xve_link_control_status_link_width_x4_v())
+                pl_link_config |= xp_pl_link_config_target_tx_width_f(
+                        xp_pl_link_config_target_tx_width_x4_v());
+        else if (link_width == xve_link_control_status_link_width_x8_v())
+                pl_link_config |= xp_pl_link_config_target_tx_width_f(
+                        xp_pl_link_config_target_tx_width_x8_v());
+        else if (link_width == xve_link_control_status_link_width_x16_v())
+                pl_link_config |= xp_pl_link_config_target_tx_width_f(
+                        xp_pl_link_config_target_tx_width_x16_v());
+        else
+                BUG();
+
+        xv_sc_dbg(LINK_SETTINGS, "  pl_link_config = 0x%08x", pl_link_config);
+        xv_sc_dbg(LINK_SETTINGS, "  Done");
+
+        xv_sc_dbg(EXEC_CHANGE, "Running link speed change...");
+
+        init_timeout(GPU_XVE_TIMEOUT_MS, &timeout);
+        while (1) {
+                gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config);
+                if (pl_link_config ==
+                    gk20a_readl(g, xp_pl_link_config_r(0)))
+                        break;
+
+                if (check_timeout(&timeout)) {
+                        err_status = -ETIMEDOUT;
+                        break;
+                }
+        }
+
+        if (err_status == -ETIMEDOUT)
+                goto done;
+
+        xv_sc_dbg(EXEC_CHANGE, "  Wrote PL_LINK_CONFIG.");
+
+        pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+
+        do {
+                pl_link_config = set_field(pl_link_config,
+                          xp_pl_link_config_ltssm_directive_m(),
+                          xp_pl_link_config_ltssm_directive_f(
+                          xp_pl_link_config_ltssm_directive_change_speed_v()));
+
+                xv_sc_dbg(EXEC_CHANGE, "  Executing change (0x%08x)!",
+                          pl_link_config);
+                gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config);
+
+                /*
+                 * Read NV_XP_PL_LINK_CONFIG until the link has swapped to
+                 * the target speed.
+                 */
+                init_timeout(GPU_XVE_TIMEOUT_MS, &timeout);
+                while (1) {
+                        pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+                        if (pl_link_config != 0xfffffff &&
+                            (xp_pl_link_config_ltssm_status_f(pl_link_config) ==
+                             xp_pl_link_config_ltssm_status_idle_v()) &&
+                            (xp_pl_link_config_ltssm_directive_f(pl_link_config) ==
+                             xp_pl_link_config_ltssm_directive_normal_operations_v()))
+                                break;
+
+                        if (check_timeout(&timeout)) {
+                                err_status = -ETIMEDOUT;
+                                xv_sc_dbg(EXEC_CHANGE, "  timeout; pl_link_config = 0x%x",
+                                        pl_link_config);
+                                break;
+                        }
+                }
+
+                xv_sc_dbg(EXEC_CHANGE, "  Change done... Checking status");
+
+                if (pl_link_config == 0xffffffff) {
+                        WARN(1, "GPU fell of PCI bus!?");
+
+                        /*
+                         * The rest of the driver is probably about to
+                         * explode...
+                         */
+                        BUG();
+                }
+
+                link_control_status =
+                        g->ops.xve.xve_readl(g, xve_link_control_status_r());
+                xv_sc_dbg(EXEC_CHANGE, "  target %d vs current %d",
+                          link_speed_setting,
+                          xve_link_control_status_link_speed_v(link_control_status));
+
+                if (err_status == -ETIMEDOUT)
+                        xv_sc_dbg(EXEC_CHANGE, "  Oops timed out?");
+        } while (attempts-- > 0 &&
+                 link_speed_setting !=
+                 xve_link_control_status_link_speed_v(link_control_status));
+
+        xv_sc_dbg(EXEC_VERIF, "Verifying speed change...");
+
+        /*
+         * Check that the new link speed is actually active. If we failed to
+         * change to the new link speed then return to the link speed setting
+         * pre-speed change.
+         */
+        new_link_speed = xve_link_control_status_link_speed_v(
+                link_control_status);
+        if (link_speed_setting != new_link_speed) {
+                u32 link_config = gk20a_readl(g, xp_pl_link_config_r(0));
+
+                xv_sc_dbg(EXEC_VERIF, "  Current and target speeds mismatch!");
+                xv_sc_dbg(EXEC_VERIF, "    LINK_CONTROL_STATUS: 0x%08x",
+                          g->ops.xve.xve_readl(g, xve_link_control_status_r()));
+                xv_sc_dbg(EXEC_VERIF, "    Link speed is %s - should be %s",
+                          xve_speed_to_str(new_link_speed),
+                          xve_speed_to_str(link_speed_setting));
+
+                link_config &= ~xp_pl_link_config_max_link_rate_m();
+                if (new_link_speed ==
+                    xve_link_control_status_link_speed_link_speed_2p5_v())
+                        link_config |= xp_pl_link_config_max_link_rate_f(
+                                xp_pl_link_config_max_link_rate_2500_mtps_v());
+                else if (new_link_speed ==
+                         xve_link_control_status_link_speed_link_speed_5p0_v())
+                        link_config |= xp_pl_link_config_max_link_rate_f(
+                                xp_pl_link_config_max_link_rate_5000_mtps_v());
+                else if (new_link_speed ==
+                         xve_link_control_status_link_speed_link_speed_8p0_v())
+                        link_config |= xp_pl_link_config_max_link_rate_f(
+                                xp_pl_link_config_max_link_rate_8000_mtps_v());
+                else
+                        link_config |= xp_pl_link_config_max_link_rate_f(
+                                xp_pl_link_config_max_link_rate_2500_mtps_v());
+
+                gk20a_writel(g, xp_pl_link_config_r(0), link_config);
+                err_status = -ENODEV;
+        } else {
+                xv_sc_dbg(EXEC_VERIF, "  Current and target speeds match!");
+                err_status = 0;
+        }
+
+done:
+        /* Restore safe timings. */
+        xv_sc_dbg(CLEANUP, "Restoring saved DL settings...");
+        gk20a_writel(g, xp_dl_mgr_r(0), saved_dl_mgr);
+        xv_sc_dbg(CLEANUP, "  Done");
+
+        xv_sc_dbg(CLEANUP, "Re-enabling ASPM settings...");
+        enable_aspm_gp106(g);
+        xv_sc_dbg(CLEANUP, "  Done");
+
+        return err_status;
+}
+
+/**
+ * Sets the PCIe link speed to @xve_link_speed which must be one of:
+ *
+ *   %GPU_XVE_SPEED_2P5
+ *   %GPU_XVE_SPEED_5P0
+ *   %GPU_XVE_SPEED_8P0
+ *
+ * If an error is encountered an appropriate error will be returned.
+ */
+static int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
+{
+        u32 current_link_speed;
+        int err;
+
+        if ((next_link_speed & GPU_XVE_SPEED_MASK) == 0)
+                return -EINVAL;
+
+        err = g->ops.xve.get_speed(g, &current_link_speed);
+        if (err)
+                return err;
+
+        /* No-op. */
+        if (current_link_speed == next_link_speed)
+                return 0;
+
+        return __do_xve_set_speed_gp106(g, next_link_speed);
+}
+
+/**
+ * Places a bitmask of available speeds for gp106 in @speed_mask.
+ */
+static void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask)
+{
+        *speed_mask = GPU_XVE_SPEED_2P5 | GPU_XVE_SPEED_5P0;
+}
+
+static ssize_t xve_link_speed_write(struct file *filp,
+                                    const char __user *buff,
+                                    size_t len, loff_t *off)
+{
+        struct gk20a *g = ((struct seq_file *)filp->private_data)->private;
+        char kbuff[16];
+        u32 buff_size, check_len;
+        u32 link_speed = 0;
+        int ret;
+
+        buff_size = min_t(size_t, 16, len);
+
+        memset(kbuff, 0, 16);
+        if (copy_from_user(kbuff, buff, buff_size))
+                return -EFAULT;
+
+        check_len = strlen("Gen1");
+        if (strncmp(kbuff, "Gen1", check_len) == 0)
+                link_speed = GPU_XVE_SPEED_2P5;
+        else if (strncmp(kbuff, "Gen2", check_len) == 0)
+                link_speed = GPU_XVE_SPEED_5P0;
+        else if (strncmp(kbuff, "Gen3", check_len) == 0)
+                link_speed = GPU_XVE_SPEED_8P0;
+        else
+                gk20a_err(g->dev, "%s: Unknown PCIe speed: %s\n",
+                          __func__, kbuff);
+
+        if (!link_speed)
+                return -EINVAL;
+
+        /* Brief pause... To help rate limit this. */
+        msleep(250);
+
+        /*
+         * And actually set the speed. Yay.
+         */
+        ret = g->ops.xve.set_speed(g, link_speed);
+        if (ret)
+                return ret;
+
+        return len;
+}
+
+static int xve_link_speed_show(struct seq_file *s, void *unused)
+{
+        struct gk20a *g = s->private;
+        u32 speed;
+        int err;
+
+        err = g->ops.xve.get_speed(g, &speed);
+        if (err)
+                return err;
+
+        seq_printf(s, "Current PCIe speed:\n  %s\n", xve_speed_to_str(speed));
+
+        return 0;
+}
+
+static int xve_link_speed_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, xve_link_speed_show, inode->i_private);
+}
+
+static const struct file_operations xve_link_speed_fops = {
+        .open = xve_link_speed_open,
+        .read = seq_read,
+        .write = xve_link_speed_write,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static int xve_available_speeds_show(struct seq_file *s, void *unused)
+{
+        struct gk20a *g = s->private;
+        u32 available_speeds;
+
+        g->ops.xve.available_speeds(g, &available_speeds);
+
+        seq_puts(s, "Available PCIe bus speeds:\n");
+        if (available_speeds & GPU_XVE_SPEED_2P5)
+                seq_puts(s, "  Gen1\n");
+        if (available_speeds & GPU_XVE_SPEED_5P0)
+                seq_puts(s, "  Gen2\n");
+        if (available_speeds & GPU_XVE_SPEED_8P0)
+                seq_puts(s, "  Gen3\n");
+
+        return 0;
+}
+
+static int xve_available_speeds_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, xve_available_speeds_show, inode->i_private);
+}
+
+static const struct file_operations xve_available_speeds_fops = {
+        .open = xve_available_speeds_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static int xve_link_control_status_show(struct seq_file *s, void *unused)
+{
+        struct gk20a *g = s->private;
+        u32 link_status;
+
+        link_status = g->ops.xve.xve_readl(g, xve_link_control_status_r());
+        seq_printf(s, "0x%08x\n", link_status);
+
+        return 0;
+}
+
+static int xve_link_control_status_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, xve_link_control_status_show, inode->i_private);
+}
+
+static const struct file_operations xve_link_control_status_fops = {
+        .open = xve_link_control_status_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static int xve_sw_init_gp106(struct device *dev)
+{
+        int err = -ENODEV;
+#ifdef CONFIG_DEBUG_FS
+        struct gk20a *g = get_gk20a(dev);
+        struct gk20a_platform *plat = gk20a_get_platform(dev);
+        struct dentry *gpu_root = plat->debugfs;
+
+        g->debugfs_xve = debugfs_create_dir("xve", gpu_root);
+        if (IS_ERR_OR_NULL(g->debugfs_xve))
+                goto fail;
+
+        /*
+         * These are just debug nodes. If they fail to get made it's not worth
+         * worrying the higher level SW.
+         */
+        debugfs_create_file("link_speed", S_IRUGO,
+                            g->debugfs_xve, g,
+                            &xve_link_speed_fops);
+        debugfs_create_file("available_speeds", S_IRUGO,
+                            g->debugfs_xve, g,
+                            &xve_available_speeds_fops);
+        debugfs_create_file("link_control_status", S_IRUGO,
+                            g->debugfs_xve, g,
+                            &xve_link_control_status_fops);
+
+        err = 0;
+fail:
+        return err;
+#else
+        return err;
+#endif
+}
+
+/*
+ * Init the HAL functions and what not. xve_sw_init_gp106() is for initializing
+ * all the other stuff like debugfs nodes, etc.
+ */
+int gp106_init_xve_ops(struct gpu_ops *gops)
+{
+        gops->xve.sw_init          = xve_sw_init_gp106;
+        gops->xve.get_speed        = xve_get_speed_gp106;
+        gops->xve.set_speed        = xve_set_speed_gp106;
+        gops->xve.available_speeds = xve_available_speeds_gp106;
+        gops->xve.xve_readl        = xve_xve_readl_gp106;
+        gops->xve.xve_writel       = xve_xve_writel_gp106;
+
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.h b/drivers/gpu/nvgpu/gp106/xve_gp106.h
new file mode 100644
index 00000000..65c75bf0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/xve_gp106.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __XVE_GP106_H__
+#define __XVE_GP106_H__
+
+#include "gk20a/gk20a.h"
+
+int gp106_init_xve_ops(struct gpu_ops *gops);
+
+/*
+ * Best guess for a reasonable timeout.
+ */
+#define GPU_XVE_TIMEOUT_MS      500
+
+/*
+ * For the available speeds bitmap.
+ */
+#define GPU_XVE_SPEED_2P5       (1 << 0)
+#define GPU_XVE_SPEED_5P0       (1 << 1)
+#define GPU_XVE_SPEED_8P0       (1 << 2)
+#define GPU_XVE_NR_SPEEDS       3
+
+#define GPU_XVE_SPEED_MASK      (GPU_XVE_SPEED_2P5 |    \
+                                 GPU_XVE_SPEED_5P0 |    \
+                                 GPU_XVE_SPEED_8P0)
+
+/*
+ * The HW uses a 2 bit field where speed is defined by a number:
+ *
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
+ *
+ * This isn't ideal for a bitmap with available speeds. So the external
+ * APIs think about speeds as a bit in a bitmap and this function converts
+ * from those bits to the actual HW speed setting.
+ *
+ * @speed_bit must have only 1 bit set and must be one of the 3 available
+ * HW speeds. Not all chips support all speeds so use available_speeds() to
+ * determine what a given chip supports.
+ */
+static inline u32 xve_speed_to_hw_speed_setting(u32 speed_bit)
+{
+        if (!speed_bit ||
+            !is_power_of_2(speed_bit) ||
+            !(speed_bit & GPU_XVE_SPEED_MASK))
+                return -EINVAL;
+
+        return ilog2(speed_bit) + 1;
+}
+
+static inline const char *xve_speed_to_str(u32 speed)
+{
+        if (!speed || !is_power_of_2(speed) ||
+            !(speed & GPU_XVE_SPEED_MASK))
+                return "Unknown ???";
+
+        return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
+               speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
+               speed & GPU_XVE_SPEED_8P0 ? "Gen3" :
+               "Unknown ???";
+}
+
+/*
+ * Debugging for the speed change.
+ */
+enum xv_speed_change_steps {
+        PRE_CHANGE = 0,
+        DISABLE_ASPM,
+        DL_SAFE_MODE,
+        CHECK_LINK,
+        LINK_SETTINGS,
+        EXEC_CHANGE,
+        EXEC_VERIF,
+        CLEANUP
+};
+
+#define xv_dbg(fmt, args...)                    \
+        gk20a_dbg(gpu_dbg_xv, fmt, ##args)
+
+#define xv_sc_dbg(step, fmt, args...)                                   \
+        xv_dbg("[%d] %15s | " fmt, step, __stringify(step), ##args)
+
+
+#endif