gpu: nvgpu: falcon bootstrap support

- Added falcon interface/HAL to bootstrap
falcon by taking boot vector as parameter
- Replaced falcon bootstrap code in multiple
files with nvgpu_flcn_bootstrap() method

JIRA NVGPU-102

Change-Id: I4324824c50c6196d8b7ecf981f815ec778da2fd9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1513643
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 1 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index ccd1b3ad..f5e7f2be 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -110,11 +110,8 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
         gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5);
 
         virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
-        gk20a_writel(g, psec_falcon_bootvec_r(),
-                        psec_falcon_bootvec_vec_f(virt_addr));
 
-        gk20a_writel(g, psec_falcon_cpuctl_r(),
-                        psec_falcon_cpuctl_startcpu_f(1));
+        nvgpu_flcn_bootstrap(&g->sec2_flcn, virt_addr);
 
         return 0;
 }
@@ -198,10 +195,6 @@ int init_sec2_setup_hw1(struct gk20a *g,
         data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f();
         gk20a_writel(g, psec_fbif_ctl_r(), data);
 
-        data = gk20a_readl(g, psec_falcon_dmactl_r());
-        data &= ~(psec_falcon_dmactl_require_ctx_f(1));
-        gk20a_writel(g, psec_falcon_dmactl_r(), data);
-
         /* setup apertures - virtual */
         gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
                         psec_fbif_transcfg_mem_type_physical_f() |