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| author | Seema Khowala <seemaj@nvidia.com> | 2018-01-23 15:16:40 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-31 16:23:30 -0500 |
| commit | 791ce6bd5480a8393c12be55e8afa459cb4dd1ff (patch) | |
| tree | c34ed1f076bec31bfc5b87a7fa490eb28a2789d6 /drivers/gpu/nvgpu/gp106 | |
| parent | 9beefc45516097db2eabf2887ff66d3334ff9fde (diff) | |
gpu: nvgpu: gv11b: enable more gr exceptions
-pd, scc, ds, ssync, mme and sked exceptions are
enabled. This will be useful for debugging
-Handle enabled interrupts
-Add gr ops to handle ssync hww. For legacy
chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr.
Since ssync hww is not enabled on legacy chips, added
ssync hww exception handling for volta only.
Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644751
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
0 files changed, 0 insertions, 0 deletions