gpu:nvgpu: PMU cleanup for ACR

- Removed ACR support code from PMU module
- Deleted ACR related ops from pmu ops
- Deleted assigning of ACR related ops
  using pmu ops during HAL init
-Removed code related to ACR bootstrap &
dependent code for all chips.

JIRA NVGPU-1147

Change-Id: I47a851a6b67a9aacde863685537c34566f97dc8d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1817990
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 0 insertions, 139 deletions

diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 9b8558db..7bb099e5 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -1191,135 +1191,3 @@ int lsf_gen_wpr_requirements(struct gk20a *g,
         plsfm->wpr_size = wpr_offset;
         return 0;
 }
-
-/*Loads ACR bin to FB mem and bootstraps PMU with bootloader code
- * start and end are addresses of ucode blob in non-WPR region*/
-int gp106_bootstrap_hs_flcn(struct gk20a *g)
-{
-        struct mm_gk20a *mm = &g->mm;
-        struct vm_gk20a *vm = mm->pmu.vm;
-        int err = 0;
-        u64 *acr_dmem;
-        u32 img_size_in_bytes = 0;
-        u32 status;
-        struct acr_desc *acr = &g->acr;
-        struct nvgpu_firmware *acr_fw = acr->acr_fw;
-        struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1;
-        u32 *acr_ucode_header_t210_load;
-        u32 *acr_ucode_data_t210_load;
-        struct wpr_carveout_info wpr_inf;
-
-        gp106_dbg_pmu(g, " ");
-
-        if (!acr_fw) {
-                /*First time init case*/
-                acr_fw = nvgpu_request_firmware(g,
-                                GM20B_HSBIN_PMU_UCODE_IMAGE,
-                                NVGPU_REQUEST_FIRMWARE_NO_SOC);
-                if (!acr_fw) {
-                        nvgpu_err(g, "pmu ucode get fail");
-                        return -ENOENT;
-                }
-                acr->acr_fw = acr_fw;
-                acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data;
-                acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data +
-                                acr->hsbin_hdr->header_offset);
-                acr_ucode_data_t210_load = (u32 *)(acr_fw->data +
-                                acr->hsbin_hdr->data_offset);
-                acr_ucode_header_t210_load = (u32 *)(acr_fw->data +
-                                acr->fw_hdr->hdr_offset);
-                img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256);
-
-                /* Lets patch the signatures first.. */
-                if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load,
-                                        (u32 *)(acr_fw->data +
-                                                acr->fw_hdr->sig_prod_offset),
-                                        (u32 *)(acr_fw->data +
-                                                acr->fw_hdr->sig_dbg_offset),
-                                        (u32 *)(acr_fw->data +
-                                                acr->fw_hdr->patch_loc),
-                                        (u32 *)(acr_fw->data +
-                                                acr->fw_hdr->patch_sig)) < 0) {
-                        nvgpu_err(g, "patch signatures fail");
-                        err = -1;
-                        goto err_release_acr_fw;
-                }
-                err = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes,
-                                &acr->acr_ucode);
-                if (err) {
-                        err = -ENOMEM;
-                        goto err_release_acr_fw;
-                }
-
-                g->ops.pmu.get_wpr(g, &wpr_inf);
-
-                acr_dmem = (u64 *)
-                        &(((u8 *)acr_ucode_data_t210_load)[
-                                        acr_ucode_header_t210_load[2]]);
-                acr->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)((u8 *)(
-                        acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]);
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_start =
-                                wpr_inf.nonwpr_base;
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_size =
-                                wpr_inf.size;
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.no_regions = 1;
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_offset = 0;
-
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_region_id = 1;
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
-                                                                                        0].region_id = 1;
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
-                        0].start_addr = (wpr_inf.wpr_base ) >> 8;
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
-                        0].end_addr = ((wpr_inf.wpr_base) + wpr_inf.size) >> 8;
-                ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
-                        0].shadowmMem_startaddress = wpr_inf.nonwpr_base >> 8;
-
-                nvgpu_mem_wr_n(g, &acr->acr_ucode, 0,
-                                acr_ucode_data_t210_load, img_size_in_bytes);
-
-                /*
-                 * In order to execute this binary, we will be using
-                 * a bootloader which will load this image into PMU IMEM/DMEM.
-                 * Fill up the bootloader descriptor for PMU HAL to use..
-                 * TODO: Use standard descriptor which the generic bootloader is
-                 * checked in.
-                 */
-
-                bl_dmem_desc->signature[0] = 0;
-                bl_dmem_desc->signature[1] = 0;
-                bl_dmem_desc->signature[2] = 0;
-                bl_dmem_desc->signature[3] = 0;
-                bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
-                flcn64_set_dma( &bl_dmem_desc->code_dma_base,
-                                                acr->acr_ucode.gpu_va);
-                bl_dmem_desc->non_sec_code_off  = acr_ucode_header_t210_load[0];
-                bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1];
-                bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5];
-                bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6];
-                bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */
-                flcn64_set_dma( &bl_dmem_desc->data_dma_base,
-                                        acr->acr_ucode.gpu_va +
-                                        (acr_ucode_header_t210_load[2]));
-                bl_dmem_desc->data_size = acr_ucode_header_t210_load[3];
-        } else {
-                acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0;
-        }
-
-        status = pmu_exec_gen_bl(g, bl_dmem_desc, 1);
-        if (status != 0) {
-                err = status;
-                goto err_free_ucode_map;
-        }
-
-        /* sec2 reset - to keep it idle */
-        nvgpu_flcn_reset(&g->sec2_flcn);
-
-        return 0;
-err_free_ucode_map:
-        nvgpu_dma_unmap_free(vm, &acr->acr_ucode);
-err_release_acr_fw:
-        nvgpu_release_firmware(g, acr_fw);
-        acr->acr_fw = NULL;
-        return err;
-}
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 94669eb3..e94bc1ea 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -618,15 +618,8 @@ static const struct gpu_ops gp106_ops = {
                 .is_lazy_bootstrap = gp106_is_lazy_bootstrap,
                 .is_priv_load = gp106_is_priv_load,
                 .prepare_ucode = gp106_prepare_ucode_blob,
-                .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn,
-                .get_wpr = gp106_wpr_info,
-                .alloc_blob_space = gp106_alloc_blob_space,
                 .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg,
                 .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc,
-                .falcon_wait_for_halt = gp106_sec2_wait_for_halt,
-                .falcon_clear_halt_interrupt_status =
-                        gp106_sec2_clear_halt_interrupt_status,
-                .init_falcon_setup_hw = init_sec2_setup_hw1,
                 .pmu_queue_tail = gk20a_pmu_queue_tail,
                 .pmu_get_queue_head = pwr_pmu_queue_head_r,
                 .pmu_mutex_release = gk20a_pmu_mutex_release,