gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL

In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h

JIRA-597

Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 10 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 795ae0d8..9b8558db 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -31,7 +31,6 @@
 #include <nvgpu/utils.h>
 
 #include "gk20a/gk20a.h"
-#include "gk20a/pmu_gk20a.h"
 
 #include "gm20b/mm_gm20b.h"
 #include "gm20b/acr_gm20b.h"
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 9c42ac3a..54648f56 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -634,6 +634,15 @@ static const struct gpu_ops gp106_ops = {
                 .pmu_queue_tail = gk20a_pmu_queue_tail,
                 .pmu_get_queue_head = pwr_pmu_queue_head_r,
                 .pmu_mutex_release = gk20a_pmu_mutex_release,
+                .pmu_is_interrupted = gk20a_pmu_is_interrupted,
+                .pmu_isr = gk20a_pmu_isr,
+                .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
+                .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,
+                .pmu_read_idle_counter = gk20a_pmu_read_idle_counter,
+                .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter,
+                .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats,
+                .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
+                .pmu_enable_irq = gk20a_pmu_enable_irq,
                 .is_pmu_supported = gp106_is_pmu_supported,
                 .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list,
                 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 61424bfe..dec35a91 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -32,10 +32,6 @@
 #include <nvgpu/hw/gp106/hw_pwr_gp106.h>
 #include <nvgpu/hw/gp106/hw_psec_gp106.h>
 
-/*Defines*/
-#define gm20b_dbg_pmu(g, fmt, arg...) \
-        nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
-
 int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
         unsigned int timeout)
 {
@@ -61,7 +57,7 @@ int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
 
         g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn,
                 FALCON_MAILBOX_1);
-        gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities);
+        nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities);
         data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0);
         if (data) {
                 nvgpu_err(g, "ACR boot failed, err %x", data);