diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-11-03 08:04:12 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:53 -0500 |
commit | 62d13e613807e9bce3a9d1ef0c61725ef3a885ce (patch) | |
tree | 0906c8ae32f9790d05685c17a413b56cb56477f9 /drivers/gpu/nvgpu/gp106 | |
parent | f41740bf08c77f54561f1b957fe552d8234524b7 (diff) |
gpu: nvgpu: RPPG support
- Added rppg module to init GR/MS-RPPG.
mscg is dependent on gr-rppg & without
gr-rppg engage mscg does not engage.
- Update pg engines HAL to return supported
pg engines & its sub features
JIRA DNVGPU-71
Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247486
(cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9)
Reviewed-on: http://git-master/r/1270762
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 70 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.h | 3 |
2 files changed, 69 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 6db80abe..6f5e71eb 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "clk/clk_mclk.h" | 24 | #include "clk/clk_mclk.h" |
25 | #include "hw_mc_gp106.h" | 25 | #include "hw_mc_gp106.h" |
26 | #include "hw_pwr_gp106.h" | 26 | #include "hw_pwr_gp106.h" |
27 | #include "lpwr/rppg.h" | ||
27 | 28 | ||
28 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 | 29 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 |
29 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | 30 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 |
@@ -174,6 +175,67 @@ static bool gp106_is_pmu_supported(struct gk20a *g) | |||
174 | return true; | 175 | return true; |
175 | } | 176 | } |
176 | 177 | ||
178 | static u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) | ||
179 | { | ||
180 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | ||
181 | return PMU_PG_FEATURE_GR_RPPG_ENABLED; | ||
182 | |||
183 | return 0; | ||
184 | } | ||
185 | |||
186 | static u32 gp106_pmu_pg_engines_list(struct gk20a *g) | ||
187 | { | ||
188 | return BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS); | ||
189 | } | ||
190 | |||
191 | static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg, | ||
192 | void *param, u32 handle, u32 status) | ||
193 | { | ||
194 | gk20a_dbg_fn(""); | ||
195 | |||
196 | if (status != 0) { | ||
197 | gk20a_err(dev_from_gk20a(g), "PG PARAM cmd aborted"); | ||
198 | return; | ||
199 | } | ||
200 | |||
201 | gp106_dbg_pmu("PG PARAM is acknowledged from PMU %x", | ||
202 | msg->msg.pg.msg_type); | ||
203 | } | ||
204 | |||
205 | static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) | ||
206 | { | ||
207 | struct pmu_gk20a *pmu = &g->pmu; | ||
208 | struct pmu_cmd cmd; | ||
209 | u32 seq; | ||
210 | u32 status; | ||
211 | |||
212 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
213 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { | ||
214 | |||
215 | status = init_rppg(g); | ||
216 | if (status != 0) { | ||
217 | gk20a_err(dev_from_gk20a(g), "RPPG init Failed"); | ||
218 | return -1; | ||
219 | } | ||
220 | |||
221 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
222 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
223 | sizeof(struct pmu_pg_cmd_gr_init_param); | ||
224 | cmd.cmd.pg.gr_init_param.cmd_type = | ||
225 | PMU_PG_CMD_ID_PG_PARAM; | ||
226 | cmd.cmd.pg.gr_init_param.sub_cmd_id = | ||
227 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | ||
228 | cmd.cmd.pg.gr_init_param.featuremask = | ||
229 | PMU_PG_FEATURE_GR_RPPG_ENABLED; | ||
230 | |||
231 | gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM"); | ||
232 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
233 | pmu_handle_param_msg, pmu, &seq, ~0); | ||
234 | } | ||
235 | |||
236 | return 0; | ||
237 | } | ||
238 | |||
177 | void gp106_init_pmu_ops(struct gpu_ops *gops) | 239 | void gp106_init_pmu_ops(struct gpu_ops *gops) |
178 | { | 240 | { |
179 | gk20a_dbg_fn(""); | 241 | gk20a_dbg_fn(""); |
@@ -195,10 +257,10 @@ void gp106_init_pmu_ops(struct gpu_ops *gops) | |||
195 | gops->pmu.lspmuwprinitdone = 0; | 257 | gops->pmu.lspmuwprinitdone = 0; |
196 | gops->pmu.fecsbootstrapdone = false; | 258 | gops->pmu.fecsbootstrapdone = false; |
197 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; | 259 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; |
198 | gops->pmu.pmu_elpg_statistics = NULL; | 260 | gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; |
199 | gops->pmu.pmu_pg_init_param = NULL; | 261 | gops->pmu.pmu_pg_init_param = gp106_pg_param_init; |
200 | gops->pmu.pmu_pg_supported_engines_list = NULL; | 262 | gops->pmu.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list; |
201 | gops->pmu.pmu_pg_engines_feature_list = NULL; | 263 | gops->pmu.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list; |
202 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | 264 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
203 | gops->pmu.dump_secure_fuses = NULL; | 265 | gops->pmu.dump_secure_fuses = NULL; |
204 | gops->pmu.reset = gp106_falcon_reset; | 266 | gops->pmu.reset = gp106_falcon_reset; |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h index 8fb4c736..a42ff620 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.h +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h | |||
@@ -14,6 +14,9 @@ | |||
14 | #ifndef __PMU_GP106_H_ | 14 | #ifndef __PMU_GP106_H_ |
15 | #define __PMU_GP106_H_ | 15 | #define __PMU_GP106_H_ |
16 | 16 | ||
17 | #define gp106_dbg_pmu(fmt, arg...) \ | ||
18 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | ||
19 | |||
17 | void gp106_init_pmu_ops(struct gpu_ops *gops); | 20 | void gp106_init_pmu_ops(struct gpu_ops *gops); |
18 | 21 | ||
19 | #endif /*__PMU_GP106_H_*/ | 22 | #endif /*__PMU_GP106_H_*/ |