gpu: nvgpu: ACR code refactor

-Created struct nvgpu_acr to hold acr module related member
 within single struct which are currently spread across multiple structs
 like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
 using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr	to perform ACR specific operation,
 currently ACR ops were part PMU which caused to have always dependence
 on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
 gk20a_remove_support() method, earlier acr cleanup was part of
 pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
 statically for chip currently in execution & assign ops to point to
 needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
 function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
 based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
 HAL for all chips to bootstrap ACR, earlier had 3 different function for
 gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.

JIRA NVGPU-1148

Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 172 insertions, 157 deletions

diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 7bb099e5..b1150e29 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -93,7 +93,7 @@ int gp106_alloc_blob_space(struct gk20a *g,
                 return 0;
         }
 
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
 
         /*
          * Even though this mem_desc wouldn't be used, the wpr region needs to
@@ -456,7 +456,7 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
         memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1));
         gr_gk20a_init_ctxsw_ucode(g);
 
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
         gp106_dbg_pmu(g, "wpr carveout base:%llx\n", (wpr_inf.wpr_base));
         gp106_dbg_pmu(g, "wpr carveout size :%x\n", (u32)wpr_inf.size);
 
@@ -479,7 +479,7 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
                 }
 
                 /*Alloc memory to hold ucode blob contents*/
-                err = g->ops.pmu.alloc_blob_space(g, plsfm->wpr_size
+                err = g->acr.alloc_blob_space(g, plsfm->wpr_size
                                                         ,&g->acr.ucode_blob);
                 if (err) {
                         goto exit_err;
@@ -557,7 +557,7 @@ int lsfm_discover_ucode_images(struct gk20a *g,
 
         /*0th index is always PMU which is already handled in earlier
         if condition*/
-        for (i = 1; i < (MAX_SUPPORTED_LSFM); i++) {
+        for (i = 1; i < g->acr.max_supported_lsfm; i++) {
                 memset(&ucode_img, 0, sizeof(ucode_img));
                 if (pmu_acr_supp_ucode_list[i](g, &ucode_img) == 0) {
                         if (ucode_img.lsf_desc != NULL) {
@@ -626,7 +626,7 @@ int gp106_pmu_populate_loader_cfg(struct gk20a *g,
          * physical addresses of each respective segment.
          */
         addr_base = p_lsfm->lsb_header.ucode_off;
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
         addr_base += (wpr_inf.wpr_base);
 
         gp106_dbg_pmu(g, "pmu loader cfg addrbase 0x%llx\n", addr_base);
@@ -701,7 +701,7 @@ int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
          * physical addresses of each respective segment.
          */
         addr_base = p_lsfm->lsb_header.ucode_off;
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
         addr_base += wpr_inf.wpr_base;
 
         gp106_dbg_pmu(g, "falcon ID %x", p_lsfm->wpr_header.falcon_id);
@@ -1017,7 +1017,7 @@ int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
 
         /* Fill in static WPR header info*/
         pnode->wpr_header.falcon_id = falcon_id;
-        pnode->wpr_header.bootstrap_owner = g->bootstrap_owner;
+        pnode->wpr_header.bootstrap_owner = g->acr.bootstrap_owner;
         pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY;
 
         pnode->wpr_header.lazy_bootstrap =
@@ -1030,6 +1030,7 @@ int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
         pnode->wpr_header.bin_version = pnode->lsb_header.signature.version;
         pnode->next = plsfm->ucode_img_list;
         plsfm->ucode_img_list = pnode;
+
         return 0;
 }
 
@@ -1191,3 +1192,121 @@ int lsf_gen_wpr_requirements(struct gk20a *g,
         plsfm->wpr_size = wpr_offset;
         return 0;
 }
+
+int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
+                struct hs_acr *acr_desc, bool is_recovery)
+{
+        struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
+        struct acr_fw_header *acr_fw_hdr = NULL;
+        struct bin_hdr *acr_fw_bin_hdr = NULL;
+        struct flcn_acr_desc_v1 *acr_dmem_desc;
+        struct wpr_carveout_info wpr_inf;
+        u32 *acr_ucode_header = NULL;
+        u32 *acr_ucode_data = NULL;
+
+        nvgpu_log_fn(g, " ");
+
+        acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
+        acr_fw_hdr = (struct acr_fw_header *)
+                (acr_fw->data + acr_fw_bin_hdr->header_offset);
+
+        acr_ucode_data = (u32 *)(acr_fw->data + acr_fw_bin_hdr->data_offset);
+        acr_ucode_header = (u32 *)(acr_fw->data + acr_fw_hdr->hdr_offset);
+
+        acr->get_wpr_info(g, &wpr_inf);
+
+        acr_dmem_desc = (struct flcn_acr_desc_v1 *)
+                &(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
+
+        acr_dmem_desc->nonwpr_ucode_blob_start = wpr_inf.nonwpr_base;
+        acr_dmem_desc->nonwpr_ucode_blob_size = wpr_inf.size;
+        acr_dmem_desc->regions.no_regions = 1U;
+        acr_dmem_desc->wpr_offset = 0U;
+
+        acr_dmem_desc->wpr_region_id = 1U;
+        acr_dmem_desc->regions.region_props[0U].region_id = 1U;
+        acr_dmem_desc->regions.region_props[0U].start_addr =
+                (wpr_inf.wpr_base) >> 8U;
+        acr_dmem_desc->regions.region_props[0U].end_addr =
+                ((wpr_inf.wpr_base) + wpr_inf.size) >> 8U;
+        acr_dmem_desc->regions.region_props[0U].shadowmMem_startaddress =
+                wpr_inf.nonwpr_base >> 8U;
+
+        return 0;
+}
+
+int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
+        struct nvgpu_acr *acr, struct hs_acr *acr_desc,
+        u32 *acr_ucode_header)
+{
+        struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
+        struct flcn_bl_dmem_desc_v1 *bl_dmem_desc =
+                &acr_desc->bl_dmem_desc_v1;
+
+        nvgpu_log_fn(g, " ");
+
+        memset(bl_dmem_desc, 0U, sizeof(struct flcn_bl_dmem_desc_v1));
+
+        bl_dmem_desc->signature[0] = 0U;
+        bl_dmem_desc->signature[1] = 0U;
+        bl_dmem_desc->signature[2] = 0U;
+        bl_dmem_desc->signature[3] = 0U;
+        bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
+
+        flcn64_set_dma(&bl_dmem_desc->code_dma_base,
+                acr_ucode_mem->gpu_va);
+
+        bl_dmem_desc->non_sec_code_off  = acr_ucode_header[0U];
+        bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
+        bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
+        bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
+        bl_dmem_desc->code_entry_point = 0U;
+
+        flcn64_set_dma(&bl_dmem_desc->data_dma_base,
+                acr_ucode_mem->gpu_va + acr_ucode_header[2U]);
+
+        bl_dmem_desc->data_size = acr_ucode_header[3U];
+
+        return 0;
+}
+
+static void nvgpu_gp106_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
+{
+        struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
+
+        nvgpu_log_fn(g, " ");
+
+        hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
+
+        hs_acr->acr_type = ACR_DEFAULT;
+        hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
+
+        hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1;
+        hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
+
+        hs_acr->acr_flcn = &g->sec2_flcn;
+        hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
+                gp106_sec2_setup_hw_and_bl_bootstrap;
+}
+
+void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
+{
+        nvgpu_log_fn(g, " ");
+
+        acr->g = g;
+
+        acr->bootstrap_owner = LSF_FALCON_ID_SEC2;
+        acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
+
+        nvgpu_gp106_acr_default_sw_init(g, &acr->acr);
+
+        acr->get_wpr_info = gp106_wpr_info;
+        acr->alloc_blob_space = gp106_alloc_blob_space;
+        acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
+        acr->patch_wpr_info_to_ucode =
+                gp106_acr_patch_wpr_info_to_ucode;
+        acr->acr_fill_bl_dmem_desc =
+                gp106_acr_fill_bl_dmem_desc;
+
+        acr->remove_support = gm20b_remove_acr_support;
+}
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h
index 3fab1509..ad004bf0 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h
@@ -63,4 +63,12 @@ int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
         void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
 int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
                 struct lsfm_managed_ucode_img_v2 *pnode);
+int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
+        struct nvgpu_acr *acr, struct hs_acr *acr_desc,
+        u32 *acr_ucode_header);
+int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
+        struct hs_acr *acr_desc, bool is_recovery);
+void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
+
 #endif /* NVGPU_ACR_GP106_H */
+
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index e94bc1ea..048c0a45 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -800,6 +800,9 @@ static const struct gpu_ops gp106_ops = {
                 .read_vin_cal_gain_offset_fuse =
                         gp106_fuse_read_vin_cal_gain_offset_fuse,
         },
+        .acr = {
+                .acr_sw_init = nvgpu_gp106_acr_sw_init,
+        },
         .get_litter_value = gp106_get_litter_value,
         .chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
 };
@@ -855,6 +858,7 @@ int gp106_init_hal(struct gk20a *g)
         gops->falcon = gp106_ops.falcon;
         gops->priv_ring = gp106_ops.priv_ring;
         gops->fuse = gp106_ops.fuse;
+        gops->acr = gp106_ops.acr;
 
         /* Lone functions */
         gops->get_litter_value = gp106_ops.get_litter_value;
@@ -875,7 +879,6 @@ int gp106_init_hal(struct gk20a *g)
         }
 
         g->pmu_lsf_pmu_wpr_init_done = 0;
-        g->bootstrap_owner = LSF_FALCON_ID_SEC2;
         gops->clk.split_rail_support = true;
         gops->clk.support_clk_freq_controller = true;
         gops->clk.support_pmgr_domain = true;
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index dec35a91..40823b69 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -32,167 +32,61 @@
 #include <nvgpu/hw/gp106/hw_pwr_gp106.h>
 #include <nvgpu/hw/gp106/hw_psec_gp106.h>
 
-int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
-        unsigned int timeout)
+int gp106_sec2_reset(struct gk20a *g)
 {
-        int status = 0;
-
-        if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) {
-                status = -EBUSY;
-        }
+        nvgpu_log_fn(g, " ");
 
-        return status;
-}
+        gk20a_writel(g, psec_falcon_engine_r(),
+                        pwr_falcon_engine_reset_true_f());
+        nvgpu_udelay(10);
+        gk20a_writel(g, psec_falcon_engine_r(),
+                        pwr_falcon_engine_reset_false_f());
 
-int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
-{
-        u32 data = 0;
-        int completion = 0;
-
-        completion = nvgpu_flcn_wait_for_halt(&g->sec2_flcn, timeout);
-        if (completion) {
-                nvgpu_err(g, "ACR boot timed out");
-                goto exit;
-        }
-
-        g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn,
-                FALCON_MAILBOX_1);
-        nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities);
-        data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0);
-        if (data) {
-                nvgpu_err(g, "ACR boot failed, err %x", data);
-                completion = -EAGAIN;
-                goto exit;
-        }
-
-        init_pmu_setup_hw1(g);
-
-exit:
-        if (completion) {
-                nvgpu_kill_task_pg_init(g);
-                nvgpu_pmu_state_change(g, PMU_STATE_OFF, false);
-                nvgpu_flcn_dump_stats(&g->sec2_flcn);
-        }
-
-        return completion;
+        nvgpu_log_fn(g, "done");
+        return 0;
 }
 
-int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
-        void *desc, u32 bl_sz)
+static int sec2_flcn_bl_bootstrap(struct gk20a *g,
+        struct nvgpu_falcon_bl_info *bl_info)
 {
-        struct gk20a *g = gk20a_from_pmu(pmu);
         struct mm_gk20a *mm = &g->mm;
-        struct nvgpu_falcon_bl_info bl_info;
-        u32 data = 0;
+        u32 data = 0U;
+        int err = 0U;
 
         nvgpu_log_fn(g, " ");
 
         /* SEC2 Config */
         gk20a_writel(g, psec_falcon_itfen_r(),
-                        gk20a_readl(g, psec_falcon_itfen_r()) |
-                        psec_falcon_itfen_ctxen_enable_f());
+                gk20a_readl(g, psec_falcon_itfen_r()) |
+                psec_falcon_itfen_ctxen_enable_f());
 
         gk20a_writel(g, psec_falcon_nxtctx_r(),
-                        pwr_pmu_new_instblk_ptr_f(
-                        nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
-                        pwr_pmu_new_instblk_valid_f(1) |
-                        nvgpu_aperture_mask(g, &mm->pmu.inst_block,
-                                pwr_pmu_new_instblk_target_sys_ncoh_f(),
-                                pwr_pmu_new_instblk_target_sys_coh_f(),
-                                pwr_pmu_new_instblk_target_fb_f()));
+                pwr_pmu_new_instblk_ptr_f(
+                nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) |
+                pwr_pmu_new_instblk_valid_f(1U) |
+                nvgpu_aperture_mask(g, &mm->pmu.inst_block,
+                        pwr_pmu_new_instblk_target_sys_ncoh_f(),
+                        pwr_pmu_new_instblk_target_sys_coh_f(),
+                        pwr_pmu_new_instblk_target_fb_f()));
 
         data = gk20a_readl(g, psec_falcon_debug1_r());
         data |= psec_falcon_debug1_ctxsw_mode_m();
         gk20a_writel(g, psec_falcon_debug1_r(), data);
 
         data = gk20a_readl(g, psec_falcon_engctl_r());
-        data |= (1 << 3);
+        data |= (1U << 3U);
         gk20a_writel(g, psec_falcon_engctl_r(), data);
 
-        bl_info.bl_src = g->acr.hsbl_ucode.cpu_va;
-        bl_info.bl_desc = desc;
-        bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
-        bl_info.bl_size = bl_sz;
-        bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag;
-        nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, &bl_info);
+        err = nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info);
 
-        return 0;
+        return err;
 }
 
-void init_pmu_setup_hw1(struct gk20a *g)
+int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
+        struct hs_acr *acr_desc,
+        struct nvgpu_falcon_bl_info *bl_info)
 {
-        struct mm_gk20a *mm = &g->mm;
-        struct nvgpu_pmu *pmu = &g->pmu;
-
-        /* PMU TRANSCFG */
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                        pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        /* PMU Config */
-        gk20a_writel(g, pwr_falcon_itfen_r(),
-                                gk20a_readl(g, pwr_falcon_itfen_r()) |
-                                pwr_falcon_itfen_ctxen_enable_f());
-        gk20a_writel(g, pwr_pmu_new_instblk_r(),
-                                pwr_pmu_new_instblk_ptr_f(
-                                        nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
-                                pwr_pmu_new_instblk_valid_f(1) |
-                                nvgpu_aperture_mask(g, &mm->pmu.inst_block,
-                                        pwr_pmu_new_instblk_target_sys_ncoh_f(),
-                                        pwr_pmu_new_instblk_target_sys_coh_f(),
-                                        pwr_pmu_new_instblk_target_fb_f()));
-
-        /*Copying pmu cmdline args*/
-        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0);
-        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
-                pmu, GK20A_PMU_TRACE_BUFSIZE);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
-                pmu, GK20A_PMU_DMAIDX_VIRT);
-        if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) {
-                g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu);
-        }
-
-        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
-                        (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
-                        g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
-
-}
-
-int gp106_sec2_reset(struct gk20a *g)
-{
-        nvgpu_log_fn(g, " ");
-
-        gk20a_writel(g, psec_falcon_engine_r(),
-                        pwr_falcon_engine_reset_true_f());
-        nvgpu_udelay(10);
-        gk20a_writel(g, psec_falcon_engine_r(),
-                        pwr_falcon_engine_reset_false_f());
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-}
-
-int init_sec2_setup_hw1(struct gk20a *g,
-                void *desc, u32 bl_sz)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err;
-        u32 data = 0;
+        u32 data = 0U;
 
         nvgpu_log_fn(g, " ");
 
@@ -219,10 +113,5 @@ int init_sec2_setup_hw1(struct gk20a *g,
                         psec_fbif_transcfg_mem_type_physical_f() |
                         psec_fbif_transcfg_target_noncoherent_sysmem_f());
 
-        err = bl_bootstrap_sec2(pmu, desc, bl_sz);
-        if (err) {
-                return err;
-        }
-
-        return 0;
+        return sec2_flcn_bl_bootstrap(g, bl_info);
 }
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
index b17028e7..f1cad65a 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
@@ -23,14 +23,10 @@
 #ifndef NVGPU_SEC2_GP106_H
 #define NVGPU_SEC2_GP106_H
 
-int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
-        unsigned int timeout);
-int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
-int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
-        void *desc, u32 bl_sz);
-void init_pmu_setup_hw1(struct gk20a *g);
-int init_sec2_setup_hw1(struct gk20a *g,
-                void *desc, u32 bl_sz);
 int gp106_sec2_reset(struct gk20a *g);
 
+int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
+        struct hs_acr *acr_desc,
+        struct nvgpu_falcon_bl_info *bl_info);
+
 #endif /* NVGPU_SEC2_GP106_H */