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authorSunny He <suhe@nvidia.com>2017-08-17 19:11:34 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-24 12:34:43 -0400
commit4b5b67d6d83430d8d670660b1dfc9cf024d60d88 (patch)
tree541a421438fe849ee4b1ab9e6bdfa9e8b6ee4485 /drivers/gpu/nvgpu/gp106
parent82ba1277f3da7379ed6b8288c04bb91db008549c (diff)
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ie37638f442fd68aca8a7ade5f297118447bdc91e Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542989 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.c26
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.h11
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c127
3 files changed, 141 insertions, 23 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
index 76e5cf89..00d6432f 100644
--- a/drivers/gpu/nvgpu/gp106/gr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -24,7 +24,7 @@
24 24
25#include <nvgpu/hw/gp106/hw_gr_gp106.h> 25#include <nvgpu/hw/gp106/hw_gr_gp106.h>
26 26
27static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num) 27bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num)
28{ 28{
29 bool valid = false; 29 bool valid = false;
30 30
@@ -53,7 +53,7 @@ static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num)
53 return valid; 53 return valid;
54} 54}
55 55
56static u32 gr_gp106_pagepool_default_size(struct gk20a *g) 56u32 gr_gp106_pagepool_default_size(struct gk20a *g)
57{ 57{
58 return gr_scc_pagepool_total_pages_hwmax_value_v(); 58 return gr_scc_pagepool_total_pages_hwmax_value_v();
59} 59}
@@ -63,7 +63,7 @@ static void gr_gp106_set_go_idle_timeout(struct gk20a *g, u32 data)
63 gk20a_writel(g, gr_fe_go_idle_timeout_r(), data); 63 gk20a_writel(g, gr_fe_go_idle_timeout_r(), data);
64} 64}
65 65
66static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr, 66int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
67 u32 class_num, u32 offset, u32 data) 67 u32 class_num, u32 offset, u32 data)
68{ 68{
69 gk20a_dbg_fn(""); 69 gk20a_dbg_fn("");
@@ -111,7 +111,7 @@ fail:
111 return -EINVAL; 111 return -EINVAL;
112} 112}
113 113
114static void gr_gp106_cb_size_default(struct gk20a *g) 114void gr_gp106_cb_size_default(struct gk20a *g)
115{ 115{
116 struct gr_gk20a *gr = &g->gr; 116 struct gr_gk20a *gr = &g->gr;
117 117
@@ -121,7 +121,7 @@ static void gr_gp106_cb_size_default(struct gk20a *g)
121 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 121 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
122} 122}
123 123
124static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, 124int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
125 struct gr_ctx_desc *gr_ctx, 125 struct gr_ctx_desc *gr_ctx,
126 struct vm_gk20a *vm, u32 class, 126 struct vm_gk20a *vm, u32 class,
127 u32 graphics_preempt_mode, 127 u32 graphics_preempt_mode,
@@ -233,19 +233,3 @@ fail_free_preempt:
233fail: 233fail:
234 return err; 234 return err;
235} 235}
236
237void gp106_init_gr(struct gk20a *g)
238{
239 struct gpu_ops *gops = &g->ops;
240
241 gp10b_init_gr(g);
242 gops->gr.is_valid_class = gr_gp106_is_valid_class;
243 gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size;
244 gops->gr.handle_sw_method = gr_gp106_handle_sw_method;
245 gops->gr.cb_size_default = gr_gp106_cb_size_default;
246 gops->gr.init_preemption_state = NULL;
247 gops->gr.set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode;
248 gops->gr.create_gr_sysfs = NULL;
249 gops->gr.set_boosted_ctx = NULL;
250 gops->gr.update_boosted_ctx = NULL;
251}
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h
index 3f49aac6..28ff56a9 100644
--- a/drivers/gpu/nvgpu/gp106/gr_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h
@@ -23,6 +23,15 @@ enum {
23 PASCAL_COMPUTE_B = 0xC1C0, 23 PASCAL_COMPUTE_B = 0xC1C0,
24}; 24};
25 25
26void gp106_init_gr(struct gk20a *g); 26bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num);
27u32 gr_gp106_pagepool_default_size(struct gk20a *g);
28int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
29 u32 class_num, u32 offset, u32 data);
30void gr_gp106_cb_size_default(struct gk20a *g);
31int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
32 struct gr_ctx_desc *gr_ctx,
33 struct vm_gk20a *vm, u32 class,
34 u32 graphics_preempt_mode,
35 u32 compute_preempt_mode);
27 36
28#endif 37#endif
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 21d5fee3..7e7fc195 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -27,6 +27,7 @@
27#include "gk20a/mc_gk20a.h" 27#include "gk20a/mc_gk20a.h"
28#include "gk20a/fb_gk20a.h" 28#include "gk20a/fb_gk20a.h"
29#include "gk20a/pmu_gk20a.h" 29#include "gk20a/pmu_gk20a.h"
30#include "gk20a/gr_gk20a.h"
30 31
31#include "gp10b/ltc_gp10b.h" 32#include "gp10b/ltc_gp10b.h"
32#include "gp10b/gr_gp10b.h" 33#include "gp10b/gr_gp10b.h"
@@ -40,6 +41,7 @@
40#include "gp10b/fifo_gp10b.h" 41#include "gp10b/fifo_gp10b.h"
41#include "gp10b/fb_gp10b.h" 42#include "gp10b/fb_gp10b.h"
42#include "gp10b/pmu_gp10b.h" 43#include "gp10b/pmu_gp10b.h"
44#include "gp10b/gr_gp10b.h"
43 45
44#include "gp106/fifo_gp106.h" 46#include "gp106/fifo_gp106.h"
45#include "gp106/regops_gp106.h" 47#include "gp106/regops_gp106.h"
@@ -51,6 +53,7 @@
51#include "gm20b/pmu_gm20b.h" 53#include "gm20b/pmu_gm20b.h"
52#include "gm20b/fb_gm20b.h" 54#include "gm20b/fb_gm20b.h"
53#include "gm20b/acr_gm20b.h" 55#include "gm20b/acr_gm20b.h"
56#include "gm20b/gr_gm20b.h"
54 57
55#include "gp106/acr_gp106.h" 58#include "gp106/acr_gp106.h"
56#include "gp106/sec2_gp106.h" 59#include "gp106/sec2_gp106.h"
@@ -221,6 +224,128 @@ static const struct gpu_ops gp106_ops = {
221 .isr_stall = gp10b_ce_isr, 224 .isr_stall = gp10b_ce_isr,
222 .isr_nonstall = gp10b_ce_nonstall_isr, 225 .isr_nonstall = gp10b_ce_nonstall_isr,
223 }, 226 },
227 .gr = {
228 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
229 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
230 .cb_size_default = gr_gp106_cb_size_default,
231 .calc_global_ctx_buffer_size =
232 gr_gp10b_calc_global_ctx_buffer_size,
233 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
234 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
235 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
236 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
237 .handle_sw_method = gr_gp106_handle_sw_method,
238 .set_alpha_circular_buffer_size =
239 gr_gp10b_set_alpha_circular_buffer_size,
240 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
241 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
242 .is_valid_class = gr_gp106_is_valid_class,
243 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
244 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
245 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
246 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
247 .init_fs_state = gr_gp10b_init_fs_state,
248 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
249 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
250 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
251 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
252 .free_channel_ctx = gk20a_free_channel_ctx,
253 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
254 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
255 .get_zcull_info = gr_gk20a_get_zcull_info,
256 .is_tpc_addr = gr_gm20b_is_tpc_addr,
257 .get_tpc_num = gr_gm20b_get_tpc_num,
258 .detect_sm_arch = gr_gm20b_detect_sm_arch,
259 .add_zbc_color = gr_gp10b_add_zbc_color,
260 .add_zbc_depth = gr_gp10b_add_zbc_depth,
261 .zbc_set_table = gk20a_gr_zbc_set_table,
262 .zbc_query_table = gr_gk20a_query_zbc,
263 .pmu_save_zbc = gk20a_pmu_save_zbc,
264 .add_zbc = gr_gk20a_add_zbc,
265 .pagepool_default_size = gr_gp106_pagepool_default_size,
266 .init_ctx_state = gr_gp10b_init_ctx_state,
267 .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx,
268 .free_gr_ctx = gr_gp10b_free_gr_ctx,
269 .update_ctxsw_preemption_mode =
270 gr_gp10b_update_ctxsw_preemption_mode,
271 .dump_gr_regs = gr_gp10b_dump_gr_status_regs,
272 .update_pc_sampling = gr_gm20b_update_pc_sampling,
273 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
274 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
275 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
276 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
277 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
278 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
279 .wait_empty = gr_gp10b_wait_empty,
280 .init_cyclestats = gr_gp10b_init_cyclestats,
281 .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
282 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
283 .bpt_reg_info = gr_gm20b_bpt_reg_info,
284 .get_access_map = gr_gp10b_get_access_map,
285 .handle_fecs_error = gr_gp10b_handle_fecs_error,
286 .handle_sm_exception = gr_gp10b_handle_sm_exception,
287 .handle_tex_exception = gr_gp10b_handle_tex_exception,
288 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
289 .enable_exceptions = gk20a_gr_enable_exceptions,
290 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
291 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
292 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
293 .record_sm_error_state = gm20b_gr_record_sm_error_state,
294 .update_sm_error_state = gm20b_gr_update_sm_error_state,
295 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
296 .suspend_contexts = gr_gp10b_suspend_contexts,
297 .resume_contexts = gr_gk20a_resume_contexts,
298 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
299 .fuse_override = gp10b_gr_fuse_override,
300 .init_sm_id_table = gr_gk20a_init_sm_id_table,
301 .load_smid_config = gr_gp10b_load_smid_config,
302 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
303 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
304 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
305 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
306 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
307 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
308 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
309 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
310 .commit_inst = gr_gk20a_commit_inst,
311 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
312 .write_pm_ptr = gr_gk20a_write_pm_ptr,
313 .init_elcg_mode = gr_gk20a_init_elcg_mode,
314 .load_tpc_mask = gr_gm20b_load_tpc_mask,
315 .inval_icache = gr_gk20a_inval_icache,
316 .trigger_suspend = gr_gk20a_trigger_suspend,
317 .wait_for_pause = gr_gk20a_wait_for_pause,
318 .resume_from_pause = gr_gk20a_resume_from_pause,
319 .clear_sm_errors = gr_gk20a_clear_sm_errors,
320 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
321 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
322 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
323 .suspend_single_sm = gk20a_gr_suspend_single_sm,
324 .suspend_all_sms = gk20a_gr_suspend_all_sms,
325 .resume_single_sm = gk20a_gr_resume_single_sm,
326 .resume_all_sms = gk20a_gr_resume_all_sms,
327 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
328 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
329 .get_sm_no_lock_down_hww_global_esr_mask =
330 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
331 .lock_down_sm = gk20a_gr_lock_down_sm,
332 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
333 .clear_sm_hww = gm20b_gr_clear_sm_hww,
334 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
335 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
336 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
337 .set_boosted_ctx = NULL,
338 .set_preemption_mode = gr_gp10b_set_preemption_mode,
339 .set_czf_bypass = gr_gp10b_set_czf_bypass,
340 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
341 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
342 .init_preemption_state = NULL,
343 .update_boosted_ctx = NULL,
344 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
345 .create_gr_sysfs = NULL,
346 .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode,
347 .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode
348 },
224 .fb = { 349 .fb = {
225 .reset = gp106_fb_reset, 350 .reset = gp106_fb_reset,
226 .init_hw = gk20a_fb_init_hw, 351 .init_hw = gk20a_fb_init_hw,
@@ -569,6 +694,7 @@ int gp106_init_hal(struct gk20a *g)
569 694
570 gops->ltc = gp106_ops.ltc; 695 gops->ltc = gp106_ops.ltc;
571 gops->ce2 = gp106_ops.ce2; 696 gops->ce2 = gp106_ops.ce2;
697 gops->gr = gp106_ops.gr;
572 gops->fb = gp106_ops.fb; 698 gops->fb = gp106_ops.fb;
573 gops->clock_gating = gp106_ops.clock_gating; 699 gops->clock_gating = gp106_ops.clock_gating;
574 gops->fifo = gp106_ops.fifo; 700 gops->fifo = gp106_ops.fifo;
@@ -618,7 +744,6 @@ int gp106_init_hal(struct gk20a *g)
618 744
619 g->pmu_lsf_pmu_wpr_init_done = 0; 745 g->pmu_lsf_pmu_wpr_init_done = 0;
620 g->bootstrap_owner = LSF_FALCON_ID_SEC2; 746 g->bootstrap_owner = LSF_FALCON_ID_SEC2;
621 gp106_init_gr(g);
622 747
623 gp10b_init_uncompressed_kind_map(); 748 gp10b_init_uncompressed_kind_map();
624 gp10b_init_kind_attr(); 749 gp10b_init_kind_attr();