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authorSunny He <suhe@nvidia.com>2017-08-11 17:43:28 -0400
committerShu Zhong <shuz@nvidia.com>2017-08-11 17:57:26 -0400
commit36c07aaf5da4d0e739c5143ed00d4ca8a2263ce1 (patch)
tree2ed7e74b2ff0b3f8dc040e981f495d18f10cab4c /drivers/gpu/nvgpu/gp106
parentf8399cfa553b6fb6d82c7fa762c372f03bf59d5f (diff)
Revert "gpu: nvgpu: Reorg fb HAL initialization"
Conflicts with gv100 changes This reverts commit 63b74d4b768e0c96367d4983fdd8f1db1d317d01. Change-Id: I5e6a1c93ff613daaa100dee436f4941af74f0ac4 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537671 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r--drivers/gpu/nvgpu/gp106/fb_gp106.c10
-rw-r--r--drivers/gpu/nvgpu/gp106/fb_gp106.h4
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c23
3 files changed, 12 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/gp106/fb_gp106.c b/drivers/gpu/nvgpu/gp106/fb_gp106.c
index 25055e79..5be7062d 100644
--- a/drivers/gpu/nvgpu/gp106/fb_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/fb_gp106.c
@@ -21,7 +21,7 @@
21#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ 21#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */
22#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ 22#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */
23 23
24void gp106_fb_reset(struct gk20a *g) 24static void gp106_fb_reset(struct gk20a *g)
25{ 25{
26 u32 val; 26 u32 val;
27 27
@@ -40,3 +40,11 @@ void gp106_fb_reset(struct gk20a *g)
40 val &= ~fb_mmu_priv_level_mask_write_violation_m(); 40 val &= ~fb_mmu_priv_level_mask_write_violation_m();
41 gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); 41 gk20a_writel(g, fb_mmu_priv_level_mask_r(), val);
42} 42}
43
44void gp106_init_fb(struct gpu_ops *gops)
45{
46 gp10b_init_fb(gops);
47
48 gops->fb.init_fs_state = NULL;
49 gops->fb.reset = gp106_fb_reset;
50}
diff --git a/drivers/gpu/nvgpu/gp106/fb_gp106.h b/drivers/gpu/nvgpu/gp106/fb_gp106.h
index 99a70d7b..87b371e1 100644
--- a/drivers/gpu/nvgpu/gp106/fb_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/fb_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -15,5 +15,5 @@
15#define FB_GP106_H 15#define FB_GP106_H
16struct gpu_ops; 16struct gpu_ops;
17 17
18void gp106_fb_reset(struct gk20a *g); 18void gp106_init_fb(struct gpu_ops *gops);
19#endif 19#endif
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 361a7b0f..4a891a82 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -24,7 +24,6 @@
24#include "gk20a/flcn_gk20a.h" 24#include "gk20a/flcn_gk20a.h"
25#include "gk20a/regops_gk20a.h" 25#include "gk20a/regops_gk20a.h"
26#include "gk20a/mc_gk20a.h" 26#include "gk20a/mc_gk20a.h"
27#include "gk20a/fb_gk20a.h"
28 27
29#include "gp10b/ltc_gp10b.h" 28#include "gp10b/ltc_gp10b.h"
30#include "gp10b/gr_gp10b.h" 29#include "gp10b/gr_gp10b.h"
@@ -36,7 +35,6 @@
36#include "gp10b/cde_gp10b.h" 35#include "gp10b/cde_gp10b.h"
37#include "gp10b/priv_ring_gp10b.h" 36#include "gp10b/priv_ring_gp10b.h"
38#include "gp10b/fifo_gp10b.h" 37#include "gp10b/fifo_gp10b.h"
39#include "gp10b/fb_gp10b.h"
40 38
41#include "gp106/fifo_gp106.h" 39#include "gp106/fifo_gp106.h"
42#include "gp106/regops_gp106.h" 40#include "gp106/regops_gp106.h"
@@ -45,7 +43,6 @@
45#include "gm20b/gr_gm20b.h" 43#include "gm20b/gr_gm20b.h"
46#include "gm20b/fifo_gm20b.h" 44#include "gm20b/fifo_gm20b.h"
47#include "gm20b/pmu_gm20b.h" 45#include "gm20b/pmu_gm20b.h"
48#include "gm20b/fb_gm20b.h"
49 46
50#include "gp106/clk_gp106.h" 47#include "gp106/clk_gp106.h"
51#include "gp106/clk_arb_gp106.h" 48#include "gp106/clk_arb_gp106.h"
@@ -213,21 +210,6 @@ static const struct gpu_ops gp106_ops = {
213 .isr_stall = gp10b_ce_isr, 210 .isr_stall = gp10b_ce_isr,
214 .isr_nonstall = gp10b_ce_nonstall_isr, 211 .isr_nonstall = gp10b_ce_nonstall_isr,
215 }, 212 },
216 .fb = {
217 .reset = gp106_fb_reset,
218 .init_hw = gk20a_fb_init_hw,
219 .init_fs_state = NULL,
220 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
221 .set_use_full_comp_tag_line =
222 gm20b_fb_set_use_full_comp_tag_line,
223 .compression_page_size = gp10b_fb_compression_page_size,
224 .compressible_page_size = gp10b_fb_compressible_page_size,
225 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
226 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
227 .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
228 .set_debug_mode = gm20b_fb_set_debug_mode,
229 .tlb_invalidate = gk20a_fb_tlb_invalidate,
230 },
231 .clock_gating = { 213 .clock_gating = {
232 .slcg_bus_load_gating_prod = 214 .slcg_bus_load_gating_prod =
233 gp106_slcg_bus_load_gating_prod, 215 gp106_slcg_bus_load_gating_prod,
@@ -497,7 +479,6 @@ int gp106_init_hal(struct gk20a *g)
497 479
498 gops->ltc = gp106_ops.ltc; 480 gops->ltc = gp106_ops.ltc;
499 gops->ce2 = gp106_ops.ce2; 481 gops->ce2 = gp106_ops.ce2;
500 gops->fb = gp106_ops.fb;
501 gops->clock_gating = gp106_ops.clock_gating; 482 gops->clock_gating = gp106_ops.clock_gating;
502 gops->fifo = gp106_ops.fifo; 483 gops->fifo = gp106_ops.fifo;
503 gops->gr_ctx = gp106_ops.gr_ctx; 484 gops->gr_ctx = gp106_ops.gr_ctx;
@@ -543,12 +524,10 @@ int gp106_init_hal(struct gk20a *g)
543 524
544 g->bootstrap_owner = LSF_FALCON_ID_SEC2; 525 g->bootstrap_owner = LSF_FALCON_ID_SEC2;
545 gp106_init_gr(g); 526 gp106_init_gr(g);
527 gp106_init_fb(gops);
546 gp106_init_mm(gops); 528 gp106_init_mm(gops);
547 gp106_init_pmu_ops(g); 529 gp106_init_pmu_ops(g);
548 530
549 gp10b_init_uncompressed_kind_map();
550 gp10b_init_kind_attr();
551
552 g->name = "gp10x"; 531 g->name = "gp10x";
553 532
554 c->twod_class = FERMI_TWOD_A; 533 c->twod_class = FERMI_TWOD_A;