diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-12-15 12:04:15 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-17 15:29:09 -0500 |
commit | 2f6698b863c9cc1db6455637b7c72e812b470b93 (patch) | |
tree | d0c8abf32d6994b9f54bf5eddafd8316e038c829 /drivers/gpu/nvgpu/gp106 | |
parent | 6a73114788ffafe4c53771c707ecbd9c9ea0a117 (diff) |
gpu: nvgpu: Make graphics context property of TSG
Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.
Bug 1842197
Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_gp106.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 |
3 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index bedc0b78..02cecf53 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c | |||
@@ -135,7 +135,7 @@ void gr_gp106_cb_size_default(struct gk20a *g) | |||
135 | } | 135 | } |
136 | 136 | ||
137 | int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | 137 | int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, |
138 | struct gr_ctx_desc *gr_ctx, | 138 | struct nvgpu_gr_ctx *gr_ctx, |
139 | struct vm_gk20a *vm, u32 class, | 139 | struct vm_gk20a *vm, u32 class, |
140 | u32 graphics_preempt_mode, | 140 | u32 graphics_preempt_mode, |
141 | u32 compute_preempt_mode) | 141 | u32 compute_preempt_mode) |
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h index 9f76e4ac..491ced4e 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h | |||
@@ -38,7 +38,7 @@ int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr, | |||
38 | u32 class_num, u32 offset, u32 data); | 38 | u32 class_num, u32 offset, u32 data); |
39 | void gr_gp106_cb_size_default(struct gk20a *g); | 39 | void gr_gp106_cb_size_default(struct gk20a *g); |
40 | int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | 40 | int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, |
41 | struct gr_ctx_desc *gr_ctx, | 41 | struct nvgpu_gr_ctx *gr_ctx, |
42 | struct vm_gk20a *vm, u32 class, | 42 | struct vm_gk20a *vm, u32 class, |
43 | u32 graphics_preempt_mode, | 43 | u32 graphics_preempt_mode, |
44 | u32 compute_preempt_mode); | 44 | u32 compute_preempt_mode); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 1498d1c0..3073668e 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -272,7 +272,6 @@ static const struct gpu_ops gp106_ops = { | |||
272 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 272 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, |
273 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, | 273 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, |
274 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | 274 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, |
275 | .free_channel_ctx = gk20a_free_channel_ctx, | ||
276 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | 275 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, |
277 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | 276 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, |
278 | .get_zcull_info = gr_gk20a_get_zcull_info, | 277 | .get_zcull_info = gr_gk20a_get_zcull_info, |