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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-08-08 13:53:25 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-09-12 16:00:19 -0400
commit89772b03cb093b3556dd4803e5a8deee60046ac9 (patch)
treec609de388b57161e9bb58ff21ef5aaf7ab663a5e /drivers/gpu/nvgpu/gp106/xve_gp106.h
parentb610bb95108afe54895219e06859cf241fabc9db (diff)
gpu: nvgpu: Move XVE debugfs code to Linux module
Move XVE debugfs initialization code to live under common/linux. JIRA NVGPU-62 Change-Id: Ic6677511d249bc0a2455dde01db5b230afc70bb1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1535133 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/xve_gp106.h')
-rw-r--r--drivers/gpu/nvgpu/gp106/xve_gp106.h51
1 files changed, 1 insertions, 50 deletions
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.h b/drivers/gpu/nvgpu/gp106/xve_gp106.h
index 37ead910..55192fc8 100644
--- a/drivers/gpu/nvgpu/gp106/xve_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/xve_gp106.h
@@ -29,55 +29,6 @@ int gp106_init_xve_ops(struct gpu_ops *gops);
29#define GPU_XVE_TIMEOUT_MS 500 29#define GPU_XVE_TIMEOUT_MS 500
30 30
31/* 31/*
32 * For the available speeds bitmap.
33 */
34#define GPU_XVE_SPEED_2P5 (1 << 0)
35#define GPU_XVE_SPEED_5P0 (1 << 1)
36#define GPU_XVE_SPEED_8P0 (1 << 2)
37#define GPU_XVE_NR_SPEEDS 3
38
39#define GPU_XVE_SPEED_MASK (GPU_XVE_SPEED_2P5 | \
40 GPU_XVE_SPEED_5P0 | \
41 GPU_XVE_SPEED_8P0)
42
43/*
44 * The HW uses a 2 bit field where speed is defined by a number:
45 *
46 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
47 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
48 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
49 *
50 * This isn't ideal for a bitmap with available speeds. So the external
51 * APIs think about speeds as a bit in a bitmap and this function converts
52 * from those bits to the actual HW speed setting.
53 *
54 * @speed_bit must have only 1 bit set and must be one of the 3 available
55 * HW speeds. Not all chips support all speeds so use available_speeds() to
56 * determine what a given chip supports.
57 */
58static inline u32 xve_speed_to_hw_speed_setting(u32 speed_bit)
59{
60 if (!speed_bit ||
61 !is_power_of_2(speed_bit) ||
62 !(speed_bit & GPU_XVE_SPEED_MASK))
63 return -EINVAL;
64
65 return ilog2(speed_bit) + 1;
66}
67
68static inline const char *xve_speed_to_str(u32 speed)
69{
70 if (!speed || !is_power_of_2(speed) ||
71 !(speed & GPU_XVE_SPEED_MASK))
72 return "Unknown ???";
73
74 return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
75 speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
76 speed & GPU_XVE_SPEED_8P0 ? "Gen3" :
77 "Unknown ???";
78}
79
80/*
81 * Debugging for the speed change. 32 * Debugging for the speed change.
82 */ 33 */
83enum xv_speed_change_steps { 34enum xv_speed_change_steps {
@@ -104,7 +55,7 @@ int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed);
104void xve_disable_aspm_gp106(struct gk20a *g); 55void xve_disable_aspm_gp106(struct gk20a *g);
105int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed); 56int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed);
106void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask); 57void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask);
107int xve_sw_init_gp106(struct gk20a *g); 58u32 xve_get_link_control_status(struct gk20a *g);
108#if defined(CONFIG_PCI_MSI) 59#if defined(CONFIG_PCI_MSI)
109void xve_rearm_msi_gp106(struct gk20a *g); 60void xve_rearm_msi_gp106(struct gk20a *g);
110#endif 61#endif