gpu: nvgpu: gp106 SEC2 falcon code update

- Added prefix gp106_ to sec2_wait_for_halt()
  & sec2_clear_halt_interrupt_status() for gp106
  SEC2 HAL
- Made changes to gp106_sec2_wait_for_halt() to
  read SEC2 falcon mailbox using common falcon
  mailbox access functions.
- Add define for falcon mailbox
- These changes are done to reuse gp106 HAL's
  for GPU_NEXT.

Change-Id: Id32a7636d775b482684212ed4ef5d01c8ea65335
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1755618
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
index 1fe94bb8..cab3ca5d 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
@@ -23,8 +23,9 @@
 #ifndef __SEC2_H_
 #define __SEC2_H_
 
-int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
-int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
+int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
+        unsigned int timeout);
+int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
 int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
         void *desc, u32 bl_sz);
 void init_pmu_setup_hw1(struct gk20a *g);